Xilinx Virtex-6 Manual page 53

Name Direction
RST Input
ADDSUB Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
Integer
WIDTH_A
Integer
WIDTH_B
Integer
LATENCY
DEVICE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MACC_MACRO: Multiple Accumulate Function implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
MACC_MACRO_inst : MACC_MACRO
generic map (
DEVICE => "VIRTEX6",
LATENCY => 3,
WIDTH_A => 25,
WIDTH_B => 18,
WIDTH_P => 48)
port map (
P => P, -- MACC output bus, width determined by WIDTH_P generic
A => A, -- MACC input A bus, width determined by WIDTH_A generic
ADDSUB => ADDSUB, -- 1-bit add/sub input, high selects add, low selects subtract
B => B, -- MACC input B bus, width determined by WIDTH_B generic
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
1
1
Allowed Values
1 to 25
1 to 18
0, 1, 2, 3, 4
"VIRTEX5",
"VIRTEX6",
"SPARTAN6"
-- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
-- Desired clock cycle latency, 1-4
-- Multiplier A-input bus width, 1-25
-- Multiplier B-input bus width, 1-18
-- Accumulator output bus width, 1-48
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Chapter 2: About Unimacros
Function
Synchronous Reset.
High sets accumulator in addition mode; low sets
accumulator in subtraction mode.
Yes
No
No
Recommended
Default Description
25
Controls the width of A input.
18
Controls the width of B input
3
Number of pipeline registers
• 1 - MREG == 1
• 2 - AREG == BREG == 1 and MREG
== 1 or MREG == 1 and PREG == 1
• 3 - AREG == BREG == 1 and MREG
== 1 and PREG == 1
• 4 - AREG == BREG == 2 and MREG
== 1 and PREG == 1
"VIRTEX6" Target hardware architecture.
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