Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual
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Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Vivado design suite 2014.2. characterization kit ibert
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Virtex-7 FPGA VC7222
Characterization Kit
IBERT
Getting Started Guide
Vivado Design Suite 2014.2
UG971 (v5.0) June 12, 2014

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Summary of Contents for Xilinx Virtex-7 FPGA VC7222 IBERT

  • Page 1 Virtex-7 FPGA VC7222 Characterization Kit IBERT Getting Started Guide Vivado Design Suite 2014.2 UG971 (v5.0) June 12, 2014...

  • Page 2: Revision History

    Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    Appendix A: Additional Resources Xilinx Resources ............65 Solution Centers .

  • Page 4: Chapter 1: Vc7222 Ibert Getting Started Guide

    VC7222 IBERT Getting Started Guide UG971 (v5.0) June 12, 2014...

  • Page 5: Overview

    Setting up the Vivado Design Suite Software, page 31 • Starting the SuperClock-2 Module, page 18 • Viewing the GTZ Transceiver Operation, page 38 • Closing the IBERT Demonstration, page 39 VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 6: Requirements

    The hardware and software required to rebuild the IBERT demonstration designs are: • Xilinx Vivado Design Suite 2014.2 • Host PC with a version of the Windows operating system supported by the Xilinx Vivado Design Suite Setting Up the VC7222 Board for GTH and GTZ IBERT Testing Caution! The VC7222 board can be damaged by electrostatic discharge (ESD).

  • Page 7: Extracting The Project Files

    Connect the SD card to the host computer. Locate the file rdf0297-vc7222-ibert-2014-2.zip on the SD memory card. Unzip the files to a working directory on the host computer. VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 8: Running The Gth Ibert Demonstration

    Note: Figure 1-1 is for reference only and might not reflect the current revision of the board. X-Ref Target - Figure 1-1 Figure 1-1: GTH Quad Location www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 9 X-Ref Target - Figure 1-3 Figure 1-3: SuperClock-2 Module Output Clock SMA Locations VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 10: Attach The Gth Quad Connector

    Figure 1-4 is for reference only and might not reflect the current version of the connector. X-Ref Target - Figure 1-4 Figure 1-4: BullsEye Connector with Elastomer Seal www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 11: Gth Transceiver Clock Connections

    Any one of the five differential outputs from the SuperClock-2 module can be used to source the GTH reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example. VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 12: Gth Tx/Rx Loopback Connections

    SMAs. X-Ref Target - Figure 1-6 Figure 1-6: SMA F-F Adapter X-Ref Target - Figure 1-7 Figure 1-7: TX-To-RX Loopback Connection Example www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 13: Configuring The Fpga

    Insert the SD card provided with the VC7222 board into the SD card reader slot located on the bottom-side (upper-right corner) of the VC7222 board. Plug the 12V output from the power adapter into connector J2 on the VC7222 board. VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 14 GTH Quad 115 GTH Quad 213 GTH Quad 214 GTH Quad 215 GTZ Quad 300A and 300B USB/UART Place the main power switch SW1 to the ON position. www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 15: Setting Up The Vivado Design Suite Software

    Start Vivado Design Suite on the host computer and click Flow > Open Hardware Manager (highlighted in Figure 1-10). X-Ref Target - Figure 1-10 Figure 1-10: Vivado Design Suite, Open Hardware Manager VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 16 An Open Hardware Target wizard starts. Click Next to run the wizard. In the Hardware Server Settings window, select Local server (target is on local machine). Click Next to open the server and connect to the Xilinx TCF JTAG cable.
  • Page 17 X-Ref Target - Figure 1-12 Figure 1-12: Select Hardware Target In the Open Hardware Target Summary window, click Finish. The wizard closes and the Vivado Design Suite opens the hardware target. VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 18: Starting The Superclock-2 Module

    Q115 IBERT design. The files are in the extracted IBERT files: ../vc7222_ibert_q115_325.bit ../vc7222_ibert_q115_debug_nets.ltx X-Ref Target - Figure 1-13 Figure 1-13: Adding the Probes File www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 19 If the FPGA was not programmed using the SD card, provide both the programming and the probes files, and then select Program Device. X-Ref Target - Figure 1-14 Figure 1-14: Program/Refresh Device VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 20 1-15). In the Run Script window, navigate to the setup_scm2_325_00.tcl script in the extracted files and click OK. X-Ref Target - Figure 1-15 Figure 1-15: Run TCL Script www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 21 ROM address changes the reference clock(s) frequency. The complete list of pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in Table 1-2. X-Ref Target - Figure 1-16 Figure 1-16: SuperClock-2 Module VIO Core VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 22 Links window by right-clicking and selecting Create Links, or by clicking the Create Links button (Figure 1-17). X-Ref Target - Figure 1-17 Figure 1-17: Serial I/O Analyzer—Create Links www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 23 RX GT from the two lists, then click the Add Link button. For this project, connect the following links (Figure 1-18): MGT_X1Y8/TX to MGT_X1Y8/RX MGT_X1Y9/TX to MGT_X1Y9/RX MGT_X1Y10/TX to MGT_X1Y10/RX MGT_X1Y11/TX to MGT_X1Y11/RX X-Ref Target - Figure 1-18 Figure 1-18: Create Links Window VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 24: Viewing Gth Transceiver Operation

    Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 3] LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTH Transceivers Product Guide for Vivado Design Suite (PG152) [Ref www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 25: Closing The Ibert Demonstration

    GTZ transceiver Quads (GTZ Quads Q300A and Q300B) on the Rev. B VC7222 board. X-Ref Target - Figure 1-20 Figure 1-20: GTZ Quad Location VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 26 IBERT demonstration. For the GTZ IBERT demonstration, the output clock frequency is preset to 255.00 MHz. See the description for connecting the SuperClock-2 module, page 9, for more details. www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 27: Attach The Gtz Quad Connector

    J57 (REFCLK0_N) → SMA connector → J8 (CLKOUT2_N) on the SuperClock-2 module J46 (REFCLK1_P) → SMA connector → J5 (CLKOUT1_P) on the SuperClock-2 module J47 (REFCLK1_N) → SMA connector → J6 (CLKOUT1_N) on the SuperClock-2 module VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 28: Gtz Tx/Rx Loopback Connections

    TX3_P → SMA F-F Adapter → RX3_P • TX3_N → SMA F-F Adapter → RX3_N • TX4_P → SMA F-F Adapter → RX4_P • TX4_N → SMA F-F Adapter → RX4_N • www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 29 VC7222 board with the cable connections required for the GTZ IBERT demonstration. X-Ref Target - Figure 1-24 Figure 1-24: Cables Connection For The GTZ IBERT Demonstration VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 30: Configuring The Fpga

    Figure 1-25: Configuration Address DIP Switch (SW8) Place the main power switch SW1 to the ON position. Table 1-1 for more details on the System ACE tool configuration. www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 31: Setting Up The Vivado Design Suite Software

    SuperClock-2 module. The SuperClock-2 module features two clock-source components: • An always-on Si570 crystal oscillator • An Si5368 jitter-attenuating clock multiplier Outputs from either source can be used to drive the transceiver reference clocks. VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 32 Q300 IBERT design. The files are in the extracted IBERT files: ../vc7222_ibert_q300_225.bit ../vc7222_ibert_q300_debug_nets.ltx X-Ref Target - Figure 1-27 Figure 1-27: Adding the Probes File www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 33 If the FPGA was not programmed using the SD card, provide both the programming and the probes files, and then select Program Device. X-Ref Target - Figure 1-28 Figure 1-28: Program/Refresh Device VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 34 1-29). In the Run Script window, navigate to the setup_scm2_255_00.tcl script in the extracted files and click OK. X-Ref Target - Figure 1-29 Figure 1-29: Run TCL Script www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 35 ROM address changes the reference clock(s) frequency. The complete list of pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in Table 1-2. X-Ref Target - Figure 1-30 Figure 1-30: SuperClock-2 Module VIO Core VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 36 Links window by right-clicking and selecting Create Links, or by clicking the Create Links button (Figure 1-31). X-Ref Target - Figure 1-31 Figure 1-31: Serial I/O Analyzer - Create Links www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 37 Lane3/TX to Lane3/RX • Lane4/TX to Lane4/RX • Lane5/TX to Lane5/RX • Lane6/TX to Lane6/RX • Lane7/TX to Lane7/RX X-Ref Target - Figure 1-32 Figure 1-32: Create Links Window VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 38: Viewing The Gtz Transceiver Operation

    Design Suite User Guide: Programming and Debugging (UG908) [Ref 3] and in LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado Design Suite (PG132) [Ref www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 39: Closing The Ibert Demonstration

    Fibrechannel PCIe Generic GigE 62.5 SATA Generic GigE SATA Generic GigE SATA Generic GigE SATA Generic GPON 187.5 74.25 Generic Interlaken 132.813 148.5 Generic Interlaken 195.313 Generic VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 40 Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 41: Chapter 2: Creating The Gth Ibert Core

    In the Vivado window, click the Manage IP icon highlighted in Figure 2-1, then select New IP Location. X-Ref Target - Figure 2-1 Figure 2-1: Initial Window, Vivado Design Suite VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 42 Part field. A Select Device window pops up. Use the drop-down menu items to narrow the choices. Select the xc7vh580thcg1155-2G device (Figure 2-2). Click OK. X-Ref Target - Figure 2-2 Figure 2-2: Select Device www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 43 IP (Figure 2-3). Click Finish. Note: Make sure the directory name does not include spaces. X-Ref Target - Figure 2-3 Figure 2-3: Manage IP Settings VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 44 In the IP Catalog window, open the Debug & Verification folder, then open the Debug folder, and double-click IBERT 7 Series GTH (Figure 2-4). X-Ref Target - Figure 2-4 Figure 2-4: IP Catalog www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 45 LineRate(Gbps) to 13.0. Use the drop-down menu to change the Refclk(MHz) to 325.00. Do not change other defaults (Figure 2-5). X-Ref Target - Figure 2-5 Figure 2-5: Customize IP - Protocol Definition VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 46 In the Protocol Selection tab, use the Protocol Selected drop-down menu next to QUAD_115 to select Custom 1/13.0 Gbps (Figure 2-6). X-Ref Target - Figure 2-6 Figure 2-6: Customize IP - Protocol Selection www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 47 (Figure 2-7). Click OK. Click Generate in the next window to generate the output products. X-Ref Target - Figure 2-7 Figure 2-7: Customize IP - Clock Settings VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 48 2-8). Specify a location to save the design, press OK, and the design opens in a new Vivado window. X-Ref Target - Figure 2-8 Figure 2-8: Open IP Example Design www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 49 OK. The SuperClock-2 Module Design Sources and Constraints are automatically added to the example design (Figure 2-9). X-Ref Target - Figure 2-9 Figure 2-9: Sources after Running add_scm2.tcl VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 50 (Figure 2-10). Click File > Save File. X-Ref Target - Figure 2-10 Figure 2-10: SuperClock-2 in the Example IBERT Wrapper www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 51 13. In the Sources window, Design Sources should now reflect that the SuperClock-2 module is part of the example IBERT design (Figure 2-11). X-Ref Target - Figure 2-11 Figure 2-11: Design Sources File Hierarchy VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 52 15. When synthesis is done, a Synthesis Complete window pops up. Select Open Synthesized Design and click OK (Figure 2-13). X-Ref Target - Figure 2-13 Figure 2-13: Synthesis Completed www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 53 Debug Core Options tab in the Cell Properties window. Change C_USER_SCAN_CHAIN* to 2 (Figure 2-14). Click File > Save Constraints. X-Ref Target - Figure 2-14 Figure 2-14: Debug Core Options for dbg_hub VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 54 18. When the Bitstream Generation Completed dialog window appears, click Cancel (Figure 2-16). X-Ref Target - Figure 2-16 Figure 2-16: Bitstream Generation Completed 19. Navigate to the ..\ibert_7series_gtz_0\ibert_7series_gtz_0_example\ibert_7serie s_gtz_0_example.runs\impl_1 directory to locate the generated bitstream. www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 55: Chapter 3: Creating The Gtz Ibert Core

    Debug folder. Double-click or right-click the IBERT 7 Series GTZ to run the GTZ configuration wizard (Figure 3-1). X-Ref Target - Figure 3-1 Figure 3-1: IP Catalog VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 56 The same frequency should be set in the setup_scm2_freq_00_xx.tcl script by modifying the set frequency statement. X-Ref Target - Figure 3-3 Figure 3-3: Customize IP - Protocol Selection www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 57 In the Lane Selection tab, select Protocol0/28.05 from the drop-down menu (Figure 3-4). Review the summary and finish the IP customization. X-Ref Target - Figure 3-4 Figure 3-4: Customize IP - GTZ Lane Selection VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 58 3-5). Specify a location to save the design, press OK, and the design opens in a new Vivado window. X-Ref Target - Figure 3-5 Figure 3-5: Open IP Example Design www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 59 OK. The SuperClock-2 Module Design Sources and Constraints are added to the example design (Figure 3-6). X-Ref Target - Figure 3-6 Figure 3-6: Sources after Running add_scm2.tcl VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 60 IBERT wrapper (Figure 3-7). Click File > Save File. X-Ref Target - Figure 3-7 Figure 3-7: SuperClock-2 in the Example IBERT Wrapper www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 61 Figure 3-8: Design Sources File Hierarchy Click Run Synthesis in the Flow Navigator, which synthesizes the complete design (Figure 3-9). X-Ref Target - Figure 3-9 Figure 3-9: Run Synthesis VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 62 When synthesis is done, a Synthesis Complete window pops up. Select Open Synthesized Design and click OK (Figure 3-10). X-Ref Target - Figure 3-10 Figure 3-10: Synthesis Completed www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 63 Debug Core Options tab in the Cell Properties window and change the C_USER_SCAN_CHAIN* option to 2 (Figure 3-11). Click File > Save Constraints. X-Ref Target - Figure 3-11 Figure 3-11: Debug Core Options for dbg_hub VC7222 IBERT Getting Started Guide www.xilinx.com Send Feedback UG971 (v5.0) June 12, 2014...
  • Page 64 12. When the Bitstream Generation Completed dialog window appears, click Cancel (Figure 3-12). X-Ref Target - Figure 3-13 Figure 3-13: Bitstream Generation Completed 13. Navigate to ..\ibert_7series_gtz_0\ibert_7series_gtz_0_example\ibert_7serie s_gtz_0_example.runs\impl_1 directory to locate the generated bitstream. www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 65: Appendix A: Additional Resources

    Virtex-7 FPGA VC7222 Characterization Kit documentation Virtex-7 FPGA VC7222 Characterization Kit Master Answer Record (AR 54015) These Xilinx documents and sites provide supplemental material useful with this guide: Virtex-7 FPGA VC7222 GTH and GTZ Transceiver Characterization Board User Guide (UG965)
  • Page 66 Appendix A: Additional Resources www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

  • Page 67: Appendix B: Warranty

    For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products. The availability of replacement products is subject to product discontinuation policies at Xilinx.
  • Page 68 Appendix B: Warranty www.xilinx.com VC7222 IBERT Getting Started Guide Send Feedback UG971 (v5.0) June 12, 2014...

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