Xilinx Virtex-6 Manual page 162

Chapter 4: About Design Elements
Available Attributes
Attribute
DEVICE_ID
ICAP_WIDTH
SIM_CFG_FILE_NAME
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ICAP_VIRTEX6: Internal Configuration Access Port
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ICAP_VIRTEX6_inst : ICAP_VIRTEX6
generic map (
DEVICE_ID => X"4244093",
ICAP_WIDTH => "X8",
SIM_CFG_FILE_NAME => "NONE"
)
port map (
BUSY => BUSY, -- 1-bit output: Busy/Ready output
O => O, -- 32-bit output: Configuration data output bus
CLK => CLK, -- 1-bit input: Clock Input
CSB => CSB, -- 1-bit input: Active-Low ICAP input Enable
I => I, -- 32-bit input: Configuration data input bus
RDWRB => RDWRB -- 1-bit input: Read/Write Select input
);
-- End of ICAP_VIRTEX6_inst instantiation
162
Data Type Allowed Values Default
Hexadecimal 32'h04244093,
32'h042CA093,
32'h042CC093,
32'h042C4093,
32'h042D0093,
32'h0423A093,
32'h0424A093,
32'h0424C093,
32'h04240093,
32'h04248093,
32'h04250093,
32'h04252093,
32'h04256093,
32'h04286093,
32'h04288093
String "X8", "X16", "X32"
String String
representing file
name and location
-- Specifies the pre-programmed Device ID value
-- Specifies the input and output data width to be used with the
-- ICAP_VIRTEX6.
-- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
-- model
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Description
32'h04244093 Specifies the pre-programmed Device ID
value to be used for simulation purposes.
"X8" Specifies the input and output data width
to be used with the ICAP_VIRTEX6.
None Specifies the Raw Bitstream (RBT) file to
be parsed by the simulation model
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013