Xilinx Virtex-6 Manual page 365

SRLC32E
Primitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock
Enable
Introduction
This design element is a variable length, 1 to 32 clock cycle shift register implemented within a single look-up
table (LUT). The shift register can be of a fixed length, static length, or it can be dynamically adjusted by changing
the address lines to the component. This element also features an active, high-clock enable and a cascading
feature in which multiple SRLC32Es can be cascaded in order to create greater shift lengths.
Port Descriptions
Port
Q
Q31
D
CLK
CE
A
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width
Output 1
Output 1
Input 1
Input 1
Input 1
Input 5
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Chapter 4: About Design Elements
Function
Shift register data output
Shift register cascaded output (connect to the D input
of a subsequent SRLC32E)
Shift register data input
Clock
Active high clock enable
Dynamic depth selection of the SRL
A=00000 ==> 1-bit shift length
A=11111 ==> 32-bit shift length
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