Design Entry Method; Instantiation Yes; Inference Recommended; Core Generator™ And Wizards No - Xilinx Virtex-6 Manual

Design Entry Method

Instantiation
Inference
CORE Generator™ and wizards
Macro support

Available Attributes

Attribute Data Type
INIT Hexadecimal

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT5_D: 5-input Look-Up Table with general and local outputs
-- Virtex-6

-- Xilinx HDL Libraries Guide, version 14.5

LUT5_D_inst : LUT5_D

generic map (

INIT => X"00000000") -- Specify LUT contents
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3, -- LUT input
I4 => I4 -- LUT input
);
-- End of LUT5_D_inst instantiation

Verilog Instantiation Template

// LUT5_D: 5-input Look-Up Table with general and local outputs
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT5_D #(
.INIT(32'h0000000)

// Specify LUT Contents

) LUT5_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3), // LUT input
.I4(I4) // LUT input
);
// End of LUT5_D_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Yes
Recommended
No
No
Allowed
Values Default
Any 32-Bit Value All zeros
www.xilinx.com
Chapter 4: About Design Elements
Description
Specifies the logic value for the look-up
tables.
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