Xilinx Virtex-6 Manual page 296

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Type
INIT Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read
-- dual-port distributed LUT RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM128X1D_inst : RAM128X1D
generic map (
INIT => X"00000000000000000000000000000000")
port map (
DPO => DPO, -- Read/Write port 1-bit output
SPO => SPO, -- Read port 1-bit output
A => A, -- Read/Write port 7-bit address input
D => D, -- RAM data input
DPRA => DPRA, -- Read port 7-bit address input
WCLK => WCLK, -- Write clock input
WE => WE -- RAM data input
);
-- End of RAM128X1D_inst instantiation
Verilog Instantiation Template
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read
// dual-port distributed LUT RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM128X1D #(
.INIT(128'h00000000000000000000000000000000)
) RAM128X1D_inst (
.DPO(DPO), // Read port 1-bit output
.SPO(SPO), // Readw/rite port 1-bit output
.A(A), // Readw/rite port 7-bit address input
.D(D), // RAM data input
.DPRA(DPRA), // Read port 7-bit address input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM128X1D_inst instantiation
296
Yes
Recommended
No
No
Allowed Values
Any 128-Bit Value
www.xilinx.com
Default Description
All zeros Specifies the initial contents of the
RAM.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013