Xilinx Virtex-6 Manual page 33

INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => DOA, -- Output port-A data, width defined by READ_WIDTH_A parameter
DOB => DOB, -- Output port-B data, width defined by READ_WIDTH_B parameter
ADDRA => ADDRA, -- Input port-A address, width defined by Port A depth
ADDRB => ADDRB, -- Input port-B address, width defined by Port B depth
CLKA => CLKA, -- 1-bit input port-A clock
CLKB => CLKB, -- 1-bit input port-B clock
DIA => DIA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
DIB => DIB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter
ENA => ENA, -- 1-bit input port-A enable
ENB => ENB, -- 1-bit input port-B enable
REGCEA => REGCEA, -- 1-bit input port-A output register enable
REGCEB => REGCEB, -- 1-bit input port-B output register enable
RSTA => RSTA, -- 1-bit input port-A reset
RSTB => RSTB, -- 1-bit input port-B reset
WEA => WEA, -- Input port-A write enable, width defined by Port A depth
WEB => WEB -- Input port-B write enable, width defined by Port B depth
);
-- End of BRAM_TDP_MACRO_inst instantiation
Verilog Instantiation Template
// BRAM_TDP_MACRO: True Dual Port RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
//////////////////////////////////////////////////////////////////////////
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
// ===============|===========|===========|===============|=============//
// 19-36 | "36Kb"
// 10-18 | "36Kb"
// 10-18 | "18Kb"
// 5-9 | "36Kb"
// 5-9 | "18Kb"
// 3-4 | "36Kb"
// 3-4 | "18Kb"
// 2 | "36Kb"
// 2 | "18Kb"
// 1 | "36Kb"
// 1 | "18Kb"
//////////////////////////////////////////////////////////////////////////
BRAM_TDP_MACRO #(
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
.DEVICE("VIRTEX6"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
.DOA_REG(0), // Optional port A output register (0 or 1)
.DOB_REG(0), // Optional port B output register (0 or 1)
.INIT_A(36'h0000000),
.INIT_B(36'h00000000), // Initial values on port B output port
.INIT_FILE ("NONE"),
.READ_WIDTH_A (0),
.READ_WIDTH_B (0),
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
| 1024 | 10-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
| 16384 | 14-bit
| 8192 | 13-bit
| 32768 | 15-bit
| 16384 | 14-bit
// Initial values on port A output port
// Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
// Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
// "GENERATE_X_ONLY" or "NONE"
www.xilinx.com
Chapter 2: About Unimacros
| 4-bit //
| 2-bit //
| 2-bit //
| 1-bit //
| 1-bit //
| 1-bit //
| 1-bit //
| 1-bit //
| 1-bit //
| 1-bit //
| 1-bit //
33