Xilinx Virtex-6 Manual page 233

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Inputs
I5
I4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
I3
I2
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
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Chapter 4: About Design Elements
I1
I0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Outputs
O
INIT[3]
INIT[4]
INIT[5]
INIT[6]
INIT[7]
INIT[8]
INIT[9]
INIT[10]
INIT[11]
INIT[12]
INIT[13]
INIT[14]
INIT[15]
INIT[16]
INIT[17]
INIT[18]
INIT[19]
INIT[20]
INIT[21]
INIT[22]
INIT[23]
INIT[24]
INIT[25]
INIT[26]
INIT[27]
INIT[28]
INIT[29]
INIT[30]
INIT[31]
INIT[32]
INIT[33]
INIT[34]
INIT[35]
INIT[36]
INIT[37]
INIT[38]
INIT[39]
233

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