Verilog Instantiation Template
// BUFIO: Local Clock Buffer
//
Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFIO BUFIO_inst (
.O(O),
// Clock buffer output
.I(I)
// Clock buffer input
);
// End of BUFIO_inst instantiation
For More Information
See the
Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
97