Xilinx Virtex-6 Manual page 326

Chapter 4: About Design Elements
Port
WEA[1:0]
WEBWE[3:0]
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
COLLISION CHECK String
DOA_REG Integer
326
Direction Width Function
Input 2 Port A byte-wide write enable. Not used when RAM_MODE=SDP.
See User Guide for WEA mapping for different port widths.
Input 4
Port B byte-wide write enable/Write enable. See User Guide for
WEBWE mapping for different port widths.
Allowed Values
"ALL",
"GENERATE_X_
ONLY", "NONE",
"WARNING_ONLY"
0, 1
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Yes
Recommended
Yes
Yes
Default Description
"ALL" Allows modification of the simulation
behavior so that if a memory collision
occurs:
• "ALL" - warning produced and
affected outputs/memory location
go unknown (X)
• "WARNING_ONLY" - warning
produced and affected
outputs/memory retain last
value
• "GENERATE_X_ONLY" - no
warning, however affected
outputs/memory go unknown (X)
• "NONE" - no warning and affected
outputs/memory retain last value
Note Setting this to a value other than
ALL can allow problems in the design
to go unnoticed during simulation.
Care should be taken when changing
the value of this attribute.
0 A value of 1 enables the output
registers to the RAM enabling quicker
clock-to-out from the RAM at the
expense of an added clock cycle of read
latency. A value of 0 allows a read in
one clock cycle but will result in slower
clock-to-out timing. Applies to port A
in TDP mode and up to 18 lower bits
(including parity bits) in SDP mode.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013