Xilinx Virtex-6 Manual page 116

Chapter 4: About Design Elements
Attribute Data Type Allowed Values Default
AREG Integer
AUTORESET_ String
PATDET
B_INPUT String
BCASCREG Integer
BREG Integer
CARRYINREG Integer
CARRYINSELREG Integer
CREG Integer
DREG Integer
INMODEREG Integer
MASK Hexa-
decimal
MREG Integer
OPMODEREG Integer
PATTERN Hexa-
decimal
PREG Integer
SEL_MASK String
SEL_PATTERN String
USE_DPORT Boolean
116
1, 0, 2 1
"NO_RESET", "NO_RESET"
"RESET_MATCH",
"RESET_NOT_
MATCH"
"DIRECT", "DIRECT"
"CASCADE"
1, 0, 2 1
1, 0, 2 1
1, 0 1
1, 0 1
1, 0 1
1, 0 1
1, 0 1
48'h000000 48'h3fff
000000 to ffffffff
48'hffffffffffff
1, 0 1
1, 0 1
48'h0000000 All zeros
00000 to
48'hffffffffffff
1, 0 1
"MASK", "C", "MASK"
"ROUNDING_
MODE1",
"ROUNDING_
MODE2"
"PATTERN", "C" "PATTERN"
FALSE, TRUE FALSE
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Description
Selects number of pipeline stages for the A input.
Automatically reset DSP slice P Register
(accumulated value or Counter Value) on the
next clock cycle if pattern detect event has
occurred on this clock cycle. The RESET_MATCH
and RESET_NOT_MATCH settings distinguish
between whether the DSP slice should cause auto
reset of P Register on the next cycle if pattern is
matched, or whenever pattern is not matched
on the current cycle but was matched on the
previous clock cycle.
Selects between B and BCIN inputs..
In conjunction with BREG, selects the number of
B input registers on B cascade BCOUT. Must be
equal to or one less than BREG value.
Selects number of pipeline stages for the B input.
Set to 1 to register the CARRYIN inputs.
Set to 1 to register the CARRYINSEL inputs.
Selects number of pipeline stages for the C input.
Selects number of pipeline stages for the D input.
Set to 1 to register the INMODE inputs.
Mask to be used for pattern detector.
Selects usage of multiplier output (M) pipeline
registers. Set to 1 to use the M pipeline registers.
Set to 1 to register the OPMODE inputs.
Pattern to be used for pattern detector.
Set to 1 to register the P outputs. The
registered outputs will include CARRYOUT,
CARRYCASCOUT, MULTSIGNOUT,
PATTERNB_DETECT, PATTERN_DETECT, and
PCOUT.
Selects mask to be used for pattern detector. The
values C and MASK are for standard uses of the
pattern detector (counter, overflow detection,
etc.). ROUNDING_MODE1 (C-bar left shifted by
1) and ROUNDING_MODE2 (C-bar left shifted
by 2) select special masks based on the optionally
registered C port. These rounding modes can be
used to implement convergent rounding in the
DSP slice using the pattern detector as described
in the Virtex-6 FPGA DSP48E1 Block User Guide.
Selects pattern to be used for pattern detector.
Selects usage of the Pre-adder and D Port.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013