Xilinx Virtex-6 Manual page 325

Port
CLKBWRCLK
DIADI[15:0]
DIBDI[15:0]
DIPADIP[1:0]
DIPBDIP[1:0]
DOADO[15:0]
DOBDO[15:0]
DOPADOP[1:0]
DOPBDOP[1:0]
ENARDEN
ENBWREN
REGCEAREGCE
REGCEB
RSTRAMARSTRAM
RSTRAMB
RSTREGARSTREG
RSTREGB
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 1 Port B clock input/Write clock input.
Input 16 Port A data input bus/Data input bus addressed by WRADDR.
When RAM_MODE=SDP, DIADI is the logical DI[15:0].
Input 16
Port B data input bus/Data input bus addressed by WRADDR.
When RAM_MODE=SDP, DIBDI is the logical DI[31:16].
Input 2
Port A parity data input bus/Data parity input bus addressed
by WRADDR. When RAM_MODE=SDP, DIPADIP is the logical
DIP[1:0].
Input 2 Port B parity data input bus/Data parity input bus addressed
by WRADDR. When RAM_MODE=SDP, DIPBDIP is the logical
DIP[3:2].
Output 16
Port A data output bus/Data output bus addressed by RDADDR.
When RAM_MODE=SDP, DOADO is the logical DO[15:0].
Output 16 Port B data output bus/Data output bus addressed by RDADDR.
When RAM_MODE=SDP, DOBDO is the logical DO[31:16].
Output 2 Port A parity data output bus/Data parity output bus addressed
by RDADDR. When RAM_MODE=SDP, DOPADOP is the logical
DOP[1:0].
Output 2
Port B parity data output bus/Data parity output bus addressed
by RDADDR. When RAM_MODE=SDP, DOPBDOP is the logical
DOP[3:2].
Input 1
Port A RAM enable/Read enable.
Input 1 Port B RAM enable/Write enable.
Input 1 Port A output register clock enable input/Output register clock
enable input (valid only when DO_REG=1).
Input 1
Port B output register clock enable (valid only when DO_REG=1
and RAM_MODE=TDP).
Input 1
Synchronous data latch set/reset to value indicated by SRVAL_A.
RSTRAMARSTRAM sets/resets the BRAM data output latch when
DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between
the internal data latch node that is reset by RSTRAMARSTRAM
and the DO output of the BRAM. This signal is RSTRAMA
on port A when RAM_MODE=TDP and RSTRAM when
RAM_MODE=SDP.
Input 1
Synchronous data latch set/reset to value indicated by SRVAL_B.
RSTRAMB sets/resets the BRAM data output latch when
DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between
the internal data latch node that is reset by RSTRAMB and the DO
output of the BRAM. Not used when RAM_MODE=SDP.
Input 1 Synchronous output register set/reset to value indicated by
SRVAL_A. RSTREGARSTREG sets/resets the output register when
DO_REG=1. RSTREG_PRIORITY_A determines if this signal gets
priority over REGCEAREGCE. This signal is RSTREGA on port A
when RAM_MODE=TDP and RSTREG when RAM_MODE=SDP.
Input 1
Synchronous output register set/reset to value indicated by
SRVAL_B. RSTREGB sets/resets the output register when
DO_REG=1. RSTREG_PRIORITY_B determines if this signal gets
priority over REGCEB. Not used when RAM_MODE=SDP.
www.xilinx.com
Chapter 4: About Design Elements
325