Xilinx Virtex-6 Manual page 7

Name Direction
WREN, Input
RDEN
SSR Input
REGCE Input
WRCLK, Input
RDCLK
Configuration Table
DATA_WIDTH
72 - 37
36 - 19
18 - 10
9 - 5
4 - 3
2
1
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the Configuration
Table above to correctly configure it to meet your design needs.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width (Bits)
1
1
1
1
BRAM_SIZE ADDR
9
36Kb
10
36Kb
9
18Kb
11
36Kb
10
18Kb
12
36Kb
11
18Kb
13
36Kb
12
18Kb
14
36Kb
13
18Kb
15
36Kb
14
18Kb
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Chapter 2: About Unimacros
Function
Write/Read enable
Output registers synchronous reset.
Output register clock enable input (valid only
when DO_REG=1)
Write/Read clock input.
WE
8
4
2
1
1
1
1
Yes
No
No
Recommended
7