Xilinx Virtex-6 Manual page 20

Chapter 2: About Unimacros
Library UNISIM;
use UNISIM.vcomponents.all;
-- BRAM_SINGLE_MACRO: Single Port RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
---------------------------------------------------------------------
-- READ_WIDTH | BRAM_SIZE | READ Depth
-- WRITE_WIDTH |
-- ============|===========|=============|============|============--
-- 37-72 | "36Kb"
-- 19-36 | "36Kb"
-- 19-36 | "18Kb"
-- 10-18 | "36Kb"
-- 10-18 | "18Kb"
-- 5-9 | "36Kb"
-- 5-9 | "18Kb"
-- 3-4 | "36Kb"
-- 3-4 | "18Kb"
-- 2 | "36Kb"
-- 2 | "18Kb"
-- 1 | "36Kb"
-- 1 | "18Kb"
---------------------------------------------------------------------
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map (
BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000",
INIT_FILE => "NONE",
WRITE_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000",
WRITE_MODE => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
20
| ADDR Width |
| WRITE Depth |
| 512 | 9-bit
| 1024 | 10-bit
| 512 | 9-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
| 16384 | 14-bit
| 8192 | 13-bit
| 32768 | 15-bit
| 16384 | 14-bit
-- Initial values on output port
-- Set/Reset value for port output
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--
| WE Width --
| 8-bit --
| 4-bit --
| 4-bit --
| 2-bit --
| 2-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013