Xilinx Virtex-6 Manual page 83

BUFGCTRL
Primitive: Global Clock MUX Buffer
Introduction
BUFGCTRL primitive is global clock buffer that is designed as a synchronous/asynchronous "glitch free" 2:1
multiplexer with two clock inputs. Unlike global clock buffers that are found in previous generation of FPGAs,
these clock buffers are designed with more control pins to provide a wider range of functionality and more
robust input switching. BUFGCTRL is not limited to clocking applications.
Port Descriptions
Port Direction
O Output
I0, I1 Input
CE0, CE1 Input
S0, S1 Input
IGNORE0, IGNORE1 Input
Design Entry Method
Instantiation
Inference
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Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1
Clock Output pin
1 (each) Clock Input:
• I0 - Clock Input Pin
• I1 - Clock Input Pin
1 (each) Clock Enable Input. The CE pins represent the clock enable pin
for each clock inputs and are used to select the clock inputs. A
setup/hold time must be specified when you are using the CE pin
to select inputs. Failure to meet this requirement could result in
a clock glitch.
1 (each) Clock Select Input. The S pins represent the clock select pin for
each clock inputs. When using the S pin as input select, there is a
setup/hold time requirement. Unlike CE pins, failure to meet this
requirement will not result in a clock glitch. However, it can cause
the output clock to appear one clock cycle later.
1 (each) Clock Ignore Input. IGNORE pins are used whenever a designer
wants to bypass the switching algorithm executed by the BUFGCTRL.
Yes
Recommended
No
No
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Chapter 4: About Design Elements
83