Xilinx Virtex-6 Manual page 322

Chapter 4: About Design Elements
RAM64X1S_1
Primitive: 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
Introduction
This design element is a 64-word by 1-bit static random access memory with synchronous write capability. When
the write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not
affected. When (WE) is High, any negative transition on (WCLK) loads the data on the data input (D) into the
word selected by the 6-bit address (A5:A0). For predictable performance, address and data inputs must be stable
before a High-to-Low (WCLK) transition. This RAM block assumes an active-Low (WCLK). However, (WCLK)
can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by
the values on the address pins.
You can initialize this element during configuration using the INIT attribute.
Logic Table
Inputs
WE (mode)
0 (read)
1 (read)
1 (read)
1 (write)
1 (read)
Data = word addressed by bits A5:A0
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
322
WCLK
X
0
1
↓
↑
Allowed Values Default
Any 64-Bit Value All zeros
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Outputs
D O
Data
X
Data
X
Data
X
D D
X Data
Yes
Recommended
No
No
Description
Initializes ROMs, RAMs, registers, and look-up
tables.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013