Xilinx Virtex-6 Manual page 160

Chapter 4: About Design Elements
Available Attributes
Attribute Data Type
IOSTANDARD String
DIFF_TERM
Boolean
IBUF_LOW_PWR Boolean
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IBUFGDS_DIFF_OUT_inst : IBUFGDS_DIFF_OUT
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT") -- Specify the input I/O standard
port map (
O => O, -- Buffer diff_p output
OB => OB, -- Buffer diff_n output
I => I, -- Diff_p buffer input (connect directly to top-level port)
IB => IB -- Diff_n buffer input (connect directly to top-level port)
);
-- End of IBUFGDS_DIFF_OUT_inst instantiation
Verilog Instantiation Template
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IBUFGDS_DIFF_OUT #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFGDS_DIFF_OUT_inst (
.O(O), // Buffer diff_p output
.OB(OB), // Buffer diff_n output
.I(I), // Diff_p buffer input (connect directly to top-level port)
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFGDS_DIFF_OUT_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
160
Allowed Values
See Data Sheet
TRUE, FALSE
TRUE, FALSE
// Differential Termination, "TRUE"/"FALSE"
www.xilinx.com
Default Description
"DEFAULT"
Assigns an I/O standard to the element.
FALSE Specifies the use of the internal differential
termination resistance.
FALSE Allows a trade off of lower power
consumption vs. highest performance
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013