Xilinx Virtex-6 Manual page 184

Chapter 4: About Design Elements
DDLY => DDLY,
OFB => OFB,
RST => RST,
-- SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
SHIFTIN1 => SHIFTIN1,
SHIFTIN2 => SHIFTIN2
);
-- End of ISERDESE1_inst instantiation
184
-- 1-bit input: Serial input data from IODELAYE1
-- 1-bit input: Data feedback input from OSERDESE1
-- 1-bit input: Active high asynchronous reset input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013