Xilinx Virtex-6 Manual page 189

KEEPER
Primitive: KEEPER Symbol
Introduction
The design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin.
For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the net
driver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.
Port Descriptions
Name Direction
O Output
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- KEEPER: I/O Buffer Weak Keeper
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
KEEPER_inst : KEEPER
port map (
O => O -- Keeper output (connect directly to top-level port)
);
-- End of KEEPER_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1-Bit Keeper output
Yes
No
No
No
www.xilinx.com
Chapter 4: About Design Elements
189