Xilinx Virtex-6 Manual page 288

Chapter 4: About Design Elements
Verilog Instantiation Template
// OSERDESE1: Output SERial/DESerializer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
OSERDESE1 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.DDR3_DATA(1),
.INIT_OQ(1'b0),
.INIT_TQ(1'b0),
.INTERFACE_TYPE("DEFAULT"), // Must leave at "DEFAULT" (MIG-only parameter)
.ODELAY_USED(0),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(1'b0),
.SRVAL_TQ(1'b0),
.TRISTATE_WIDTH(4)
)
OSERDESE1_inst (
// MIG-only Signals: 1-bit (each) output: Do not use unless generated by MIG
.OCBEXTEND(OCBEXTEND),
// Outputs: 1-bit (each) output: Serial output ports
.OFB(OFB),
.OQ(OQ),
.TFB(TFB),
.TQ(TQ),
// SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(SHIFTOUT1),
.SHIFTOUT2(SHIFTOUT2),
// Clocks: 1-bit (each) input: OSERDESE1 clock input ports
.CLK(CLK),
.CLKDIV(CLKDIV),
// Control Signals: 1-bit (each) input: Clock enable and reset input ports
.OCE(OCE),
.RST(RST),
.TCE(TCE),
// D1 - D6: 1-bit (each) input: Parallel data inputs
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.D5(D5),
.D6(D6),
// MIG-only Signals: 1-bit (each) input: Do not use unless generated by MIG
.CLKPERF(CLKPERF),
.CLKPERFDELAY(CLKPERFDELAY), // 1-bit input: Ground input (MIG-only connected signal)
.ODV(ODV),
.WC(WC),
// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(SHIFTIN1),
.SHIFTIN2(SHIFTIN2),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(T1),
.T2(T2),
.T3(T3),
.T4(T4)
);
// End of OSERDESE1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
288
// "SDR" or "DDR"
// "BUF", "SDR" or "DDR"
// Parallel data width (1-8,10)
// Must leave at 1 (MIG-only parameter)
// Initial value of OQ output (0/1)
// Initial value of TQ output (0/1)
// Must leave at 0 (MIG-only parameter)
// "MASTER" or "SLAVE"
// OQ output value when SR is used (0/1)
// TQ output value when SR is used (0/1)
// Parallel to serial 3-state converter width (1 or 4)
// 1-bit output: Leave unconnected (MIG-only connected signal)
// 1-bit output: Data feedback output to ISERDESE1
// 1-bit output: Data output (connect to I/O port)
// 1-bit output: 3-state control output
// 1-bit output: 3-state path output
// 1-bit output: Connect to SHIFTIN1 of slave or unconnected
// 1-bit output: Connect to SHIFTIN2 of slave or unconnected
// 1-bit input: High-speed clock input
// 1-bit input: Divided clock input
// 1-bit input: Active high clock data path enable input
// 1-bit input: Active high reset input
// 1-bit input: Active high clock enable input for 3-state
// 1-bit input: Ground input (MIG-only connected signal)
// 1-bit input: Ground input (MIG-only connected signal)
// 1-bit input: Ground input (MIG-only connected signal)
// 1-bit input: Connect to SHIFTOUT1 of master or GND
// 1-bit input: Connect to SHIFTOUT2 of master or GND
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013