Xilinx Virtex-6 Manual page 255

MMCM_BASE
Primitive: Mixed signal block designed to support clock network deskew, frequency
synthesis, and jitter reduction.
Introduction
This component is a mixed signal block designed to support clock network deskew, frequency synthesis,
and jitter reduction. The seven "O" counters can be independently programmed which means O0 could be
programmed to do a divide by 2 while O1 is programmed to do a divide by 3. The only constraint is that the
VCO operating frequency must be the same for all the output counters since a single VCO drives all the counters.
The CLKFBOUT and CLKFBOUTB pins can be used to drive logic but it must be equal to the CLKin frequency.
Port Descriptions
Port
CLKFBIN
CLKFBOUT
CLKFBOUTB
CLKIN1
CLKOUT[0:6]
CLKOUT[0:3]B
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 1
Feedback clock input.
Output 1
Dedicated MMCM feedback output.
Output 1
Inverted MMCM feedback clock output.
Input 1
General clock input.
Output
7, 1-bit User configurable clock outputs (0 through 6) that can be divided
versions of the VCO phase outputs (user controllable) from 1
(bypassed) to 128. The output clocks are phase aligned to each
other (unless phase shifted) and aligned to the input clock with a
proper feedback configuration.
Output 4, 1-bit Inverted CLKOUT[0:3].
www.xilinx.com
Chapter 4: About Design Elements
255