Xilinx Virtex-6 Manual page 166

Chapter 4: About Design Elements
-- End of IDDR_inst instantiation
Verilog Instantiation Template
// IDDR: Input Double Data Rate Input Register with Set, Reset
// and Clock Enable.
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IDDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst (
.Q1(Q1), // 1-bit output for positive edge of clock
.Q2(Q2), // 1-bit output for negative edge of clock
.C(C), // 1-bit clock input
.CE(CE), // 1-bit clock enable input
.D(D), // 1-bit DDR data input
.R(R), // 1-bit reset
.S(S) // 1-bit set
);
// End of IDDR_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
166
// or "SAME_EDGE_PIPELINED"
www.xilinx.com
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013