Xilinx Virtex-6 Manual page 312

Chapter 4: About Design Elements
Available Attributes
Attribute Data Type
INIT_00
Hexadecimal
INIT_01
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM32X2S_inst : RAM32X2S
generic map (
INIT_00 => X"00000000", --
INIT_01 => X"00000000") --
port map (
O0 => O0, -- RAM data[0] output
O1 => O1, -- RAM data[1] output
A0 => A0, -- RAM address[0] input
A1 => A1, -- RAM address[1] input
A2 => A2, -- RAM address[2] input
A3 => A3, -- RAM address[3] input
A4 => A4, -- RAM address[4] input
D0 => D0, -- RAM data[0] input
D1 => D1, -- RAM data[1] input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM32X2S_inst instantiation
Verilog Instantiation Template
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM32X2S #(
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
.INIT_01(32'h00000000)
) RAM32X2S_inst (
.O0(O0), // RAM data[0] output
.O1(O1), // RAM data[1] output
.A0(A0), // RAM address[0] input
.A1(A1), // RAM address[1] input
.A2(A2), // RAM address[2] input
.A3(A3), // RAM address[3] input
.A4(A4), // RAM address[4] input
.D0(D0), // RAM data[0] input
.D1(D1), // RAM data[1] input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM32X2S_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
312
Allowed Values
Any 32-Bit Value
Any 32-Bit Value
INIT for bit 0 of RAM
INIT for bit 1 of RAM
// INIT for bit 1 of RAM
www.xilinx.com
Default Descriptions
All zeros INIT for bit 0 of RAM.
All zeros INIT for bit 1 of RAM.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013