Xilinx Virtex-6 Manual page 183

Attribute
SERDES_MODE
SRVAL_Q1 - SRVAL_Q4
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ISERDESE1: Input SERial/DESerializer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ISERDESE1_inst : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 4,
DYN_CLKDIV_INV_EN => FALSE, -- Enable DYNCLKDIVINVSEL inversion (TRUE/FALSE)
DYN_CLK_INV_EN => FALSE,
-- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- "MEMORY", "MEMORY_DDR3", "MEMORY_QDR", "NETWORKING", or "OVERSAMPLE"
IOBDELAY => "NONE",
NUM_CE => 2,
OFB_USED => FALSE,
SERDES_MODE => "MASTER",
-- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
O => O,
-- Q1 - Q6: 1-bit (each) output: Registered data outputs
Q1 => Q1,
Q2 => Q2,
Q3 => Q3,
Q4 => Q4,
Q5 => Q5,
Q6 => Q6,
-- SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
SHIFTOUT1 => SHIFTOUT1,
SHIFTOUT2 => SHIFTOUT2,
BITSLIP => BITSLIP,
-- CE1, CE2: 1-bit (each) input: Data register clock enable inputs
CE1 => CE1,
CE2 => CE2,
-- Clocks: 1-bit (each) input: ISERDESE1 clock input ports
CLK => CLK,
CLKB => CLKB,
CLKDIV => CLKDIV,
OCLK => OCLK,
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
DYNCLKDIVSEL => DYNCLKDIVSEL, -- 1-bit input: Dynamic CLKDIV inversion input
DYNCLKSEL => DYNCLKSEL,
-- Input Data: 1-bit (each) input: ISERDESE1 data input ports
D => D,
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Data Type Allowed Values
String "MASTER",
"SLAVE"
Binary 1'b0 to 1'b1
-- "SDR" or "DDR"
-- Parallel data width (2-8, 10)
-- Enable DYNCLKINVSEL inversion (TRUE/FALSE)
-- "NONE", "IBUF", "IFD", "BOTH"
-- Number of clock enables (1 or 2)
-- Select OFB path (TRUE/FALSE)
-- "MASTER" or "SLAVE"
-- 1-bit output: Combinatorial output
-- 1-bit input: Bitslip enable input
-- 1-bit input: High-speed clock input
-- 1-bit input: High-speed secondary clock input
-- 1-bit input: Divided clock input
-- 1-bit input: High speed output clock input used when
-- INTERFACE_TYPE="MEMORY"
-- 1-bit input: Dynamic CLK/CLKB inversion input
-- 1-bit input: Data input
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Chapter 4: About Design Elements
Default Description
"MASTER" Specify whether the ISERDES is
operating in master or slave modes
when cascaded width expansion.
1'b0 Defines the value of Q outputs when
the SR is invoked.
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