Xilinx Virtex-6 Manual page 74

Chapter 4: About Design Elements
BSCAN_VIRTEX6
Primitive: Virtex®-6 JTAG Boundary-Scan Logic Access Circuit
Introduction
This design element allows access to and from internal logic by the JTAG Boundary Scan logic controller. This
allows for communication between the internal running design and the dedicated JTAG pins of the FPGA.
Each instance of this design element will handle one JTAG USER instruction (USER1 through USER4) as set with
the JTAG_CHAIN attribute. To handle all four USER instuctions, instantiate four of these elements and set the
JTAG_CHAIN attribute appropriately.
Note For specific information on boundary scan for an architecture, see the Programmable Logic Data Sheet
for this element.
Port Descriptions
Port Direction
CAPTURE Output
DRCK Output
RESET Output
RUNTEST Output
SEL Output
SHIFT Output
TCK Output
TDI Output
TDO Input
TMS Output
UPDATE Output
74
Width Function
1
Scan Data Register Capture instruction.
1
Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles
during the CAPTUREDR and SHIFTDR states.
1 Scan register reset instruction.
1 Asserted when TAP controller is in Run Test Idle state.
1 Scan mode Select instruction.
1 Scan Chain Shift instruction.
1 Scan Clock. Fabric connection to TAP Clock pin.
1 Scan Chain Output. Mirror of TDI input pin to FPGA
1 Scan Chain Input.
1 Test Mode Select. Fabric connection to TAP.
1 Scan Register Update instruction.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013