Xilinx Virtex-6 Manual page 167

IDDR_2CLK
Primitive: Input Dual Data-Rate Register with Dual Clock Inputs
Introduction
This design element is a dedicated input register designed to receive external dual data rate (DDR) signals into
Xilinx® FPGAs. In general, you should only use the IDDR_2CLK for applications in which two clocks are
required to capture the rising and falling data for DDR applications.
• OPPOSITE_EDGE mode - Data is presented in the classic DDR methodology. Given a DDR data and
clock at pin D and C respectively, Q1 changes after every positive edge of clock C, and Q2 changes after
every positive edge of clock CB.
• SAME_EDGE mode - Data is still presented by positive edges of each clock. However, an extra register has
been placed in front of the CB clocked data register. This extra register is clocked with positive clock edge of
clock signal C. As a result, DDR data is now presented into the FPGA fabric at the positive edge of clock C.
However, because of this feature, the data pair appears to be "separated." Q1 and Q2 no longer have pair 1 and
2. Instead, the first pair presented is Pair 1 and DON'T CARE, followed by Pair 2 and 3 at the next clock cycle.
• SAME_EDGE_PIPELINED mode - Presents data in a similar fashion as the SAME_EDGE mode. In order to
avoid the "separated" effect of the SAME_EDGE mode, an extra register has been placed in front of the C
clocked data register. A data pair now appears at the Q1 and Q2 pin at the same time during the positive edge
of C. However, using this mode, costs you an additional cycle of latency for Q1 and Q2 signals to change.
IDDR also works with SelectIO™ features, such as the IODELAY.
Port Descriptions
Port Direction
Q1 : Q2 Output
Input
C
CB Input
CE Input
D Input
R Input
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1 These pins are the IDDR output that connects to the FPGA
fabric. Q1 is the first data pair and Q2 is the second data pair.
1
Primary clock input pin used to capture the positive edge
data.
1 Secondary clock input pin (typically 180 degrees out of
phase with the primary clock) used to capture the negative
edge data.
1
When asserted Low, this port disables the output clock at
port O.
1 This pin is where the DDR data is presented into the IDDR
module.
This pin connects to a top-level input or bi-directional
port, and IODELAY configured for an input delay or to an
appropriate input or bidirectional buffer.
1
Active high reset forcing Q1 and Q2 to a logic zero. Can
be synchronous or asynchronous based on the SRTYPE
attribute.
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Chapter 4: About Design Elements
167