Xilinx Virtex-6 Manual page 68

Chapter 3: Functional Categories
Design Element
BUFHCE
BUFIO
BUFIODQS
BUFR
IBUFDS_GTXE1
MMCM_ADV
MMCM_BASE
Design Element
BSCAN_VIRTEX6
CAPTURE_VIRTEX6
DNA_PORT
EFUSE_USR
FRAME_ECC_VIRTEX6
ICAP_VIRTEX6
JTAG_SIM_VIRTEX6
SIM_CONFIG_V6
SIM_CONFIG_V6_SERIAL
STARTUP_VIRTEX6
USR_ACCESS_VIRTEX6
Design Element
DCIRESET
GTHE1_QUAD
GTXE1
IBUF
IBUFDS
IBUFDS_DIFF_OUT
IBUFDS_GTHE1
68
Description
Primitive: Clock buffer for a single clocking region with
clock enable
Primitive: Local Clock Buffer for I/O
Primitive: Differential Clock Input for Transceiver
Reference Clocks
Primitive: Regional Clock Buffer for I/O and Logic
Resources
Primitive: Differential Clock Input for the Transceiver
Reference Clocks
Primitive: MMCM is a mixed signal block designed to
support clock network deskew, frequency synthesis, and
jitter reduction.
Primitive: Mixed signal block designed to support clock
network deskew, frequency synthesis, and jitter reduction.
Config/BSCAN Components
Description
Primitive: Virtex®-6 JTAG Boundary-Scan Logic Access
Circuit
Primitive: Virtex®-6 Readback Register Capture Control
Primitive: Device DNA Data Access Port
Primitive: 32-bit non-volatile design ID
Primitive: Virtex®-6 Configuration Frame Error Detection
and Correction Circuitry
Primitive: Internal Configuration Access Port
Simulation: JTAG TAP Controller Simulation Model
Simulation: Configuration Simulation Model
Simulation: Serial Configuration Simulation Model
Primitive: Virtex®-6 Configuration Start-Up Sequence
Interface
Primitive: Virtex-6 User Access Register
I/O Components
Description
Primitive: DCI State Machine Reset (After Configuration
Has Been Completed)
Primitive: Gigabit Transceiver
Primitive: Gigabit Transceiver
Primitive: Input Buffer
Primitive: Differential Signaling Input Buffer
Primitive: Signaling Input Buffer with Differential Output
Primitive: Differential Clock Input for the GTH Transceiver
Reference Clocks
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013