Xilinx Virtex-6 Manual page 111

Available Attributes
Data
Attribute Type
Hexa-
SIM_DNA_VALUE
decimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DNA_PORT: Device DNA Access Port
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
DNA_PORT_inst : DNA_PORT
generic map (
SIM_DNA_VALUE => X"000000000000000"
)
port map (
DOUT => DOUT, -- 1-bit output: DNA output data
CLK => CLK, -- 1-bit input: Clock input
DIN => DIN, -- 1-bit input: User data input pin
READ => READ, -- 1-bit input: Active high load DNA, active low read input
SHIFT => SHIFT -- 1-bit input: Active high shift enable input
);
-- End of DNA_PORT_inst instantiation
Verilog Instantiation Template
// DNA_PORT: Device DNA Access Port
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
DNA_PORT #(
.SIM_DNA_VALUE(57'h000000000000000)
)
DNA_PORT_inst (
.DOUT(DOUT), // 1-bit output: DNA output data
.CLK(CLK), // 1-bit input: Clock input
.DIN(DIN), // 1-bit input: User data input pin
.READ(READ), // 1-bit input: Active high load DNA, active low read input
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input
);
// End of DNA_PORT_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
57'h00000000 57'h00000000
0000000 to 0000000
57'h1ffffffffffffff
-- Specifies the Pre-programmed factory ID value
// Specifies the Pre-programmed factory ID value
www.xilinx.com
Chapter 4: About Design Elements
Description
Specifies the Pre-programmed factory ID
value.
Sheets).
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