Xilinx Virtex-6 Manual page 174

Chapter 4: About Design Elements
IOBUFDS
Primitive: 3-State Differential Signaling I/O Buffer with Active Low Output Enable
Introduction
The design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS, a
design level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" and
the other the "slave." The master and the slave are opposite phases of the same logical signal (for example,
MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to help
improve signal integrity and reduce external components. Also available is a programmable delay is to assist in
the capturing of incoming data to the device.
Logic Table
Inputs
I T
X 1
0 0
I 0
Port Descriptions
Port Direction
O Output
IO Inout
IOB Inout
I Input
T Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
174
Bidirectional
IO IOB
Z Z
0 1
1 0
Width Function
1 Buffer output
1 Diff_p inout
1 Diff_n inout
1 Buffer input
1 3-state enable input
Recommended
No
No
No
www.xilinx.com
Outputs
O
No Change
0
1
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013