Xilinx Virtex-6 Manual page 249

Port
CLKINSEL
CLKINSTOPPED
CLKIN1
CLKIN2
CLKOUT[0:6]
CLKOUT[0:3]B
DADDR[6:0]
DCLK
DEN
DI[15:0]
DO[15:0]
DRDY
DWE
LOCKED
PSCLK
PSDONE
PSEN
PSINCDEC
PWRDWN
RST
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 1 Signal controls the state of the input MUX, High = CLKIN1, Low
= CLKIN2.
Output 1
Status pin indicating that the input clock has stopped.
Input 1
General clock input.
Input 1
Secondary clock input for the MMCM reference clock.
Output
7, 1-bit User configurable clock outputs (0 through 6) that can be divided
versions of the VCO phase outputs (user controllable) from 1
(bypassed) to 128. The output clocks are phase aligned to each
other (unless phase shifted) and aligned to the input clock with a
proper feedback configuration.
Output 4, 1-bit Inverted CLKOUT[0:3].
Input 7 The dynamic reconfiguration address (DADDR) input
bus provides a reconfiguration address for the dynamic
reconfiguration. When not used, all bits must be assigned zeros.
Input 1 The DCLK signal is the reference clock for the dynamic
reconfiguration port.
Input 1 The dynamic reconfiguration enable (DEN) provides the enable
control signal to access the dynamic reconfiguration feature.
When the dynamic reconfiguration feature is not used, DEN must
be tied Low.
Input 16
The dynamic reconfiguration data input (DI) bus provides
reconfiguration data. When not used, all bits must be set to zero.
Output 16
The dynamic reconfiguration output bus provides MMCM data
output when using dynamic reconfiguration.
Output 1 The dynamic reconfiguration ready (DRDY) output provides
the response to the DEN signal for the MMCMs dynamic
reconfiguration feature.
Input 1
The dynamic reconfiguration write enable (DWE) input pin
provides the write enable control signal to write the DI data into
the DADDR address. When not used, it must be tied Low.
1
Output An output from the MMCM that indicates when the MMCM
has achieved phase alignment within a predefined window and
frequency matching within a predefined PPM range. The MMCM
automatically locks after power on. No extra reset is required.
LOCKED will be deasserted if the input clock stops or the phase
alignment is violated (e.g., input clock phase shift). The MMCM
automatically reacquires lock after LOCKED is deasserted.
Input 1
Phase shift clock.
Output 1
Phase shift done.
Input 1
Phase shift enable.
Input 1
Phase shift Increment/Decrement control.
Input 1
Powers down instantiated but unused MMCMs.
Input 1
Asynchronous reset signal.The MMCM will synchronously
re-enable itself when this signal is released (i.e., MMCM
re-enabled). A reset is not required when the input clock
conditions change (e.g., frequency).
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Chapter 4: About Design Elements
249