Xilinx Virtex-6 Manual page 76

Chapter 4: About Design Elements
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller
.TCK(TCK), // 1-bit output: Scan Clock output. Fabric connection to TAP Clock pin.
.TDI(TDI), // 1-bit output: TDI output from TAP controller
.TMS(TMS), // 1-bit output: Test Mode Select input. Fabric connection to TAP.
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
.TDO(TDO) // 1-bit input: Data input for USER function
);
// End of BSCAN_VIRTEX6_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
76
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013