Xilinx Virtex-6 Manual page 120

Chapter 4: About Design Elements
.RSTA(RSTA),
.RSTALLCARRYIN(RSTALLCARRYIN),
.RSTALUMODE(RSTALUMODE),
.RSTB(RSTB),
.RSTC(RSTC),
.RSTCTRL(RSTCTRL),
.RSTD(RSTD),
.RSTM(RSTM),
.RSTP(RSTP)
);
// End of DSP48E1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
120
// 1-bit input: Reset input for AREG
// 1-bit input: Reset input for CARRYINREG
// 1-bit input: Reset input for ALUMODEREG
// 1-bit input: Reset input for BREG
// 1-bit input: Reset input for CREG
// 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
// 1-bit input: Reset input for DREG and ADREG
// 1-bit input: Reset input for MREG
// 1-bit input: Reset input for PREG
Sheets).
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013