Xilinx Virtex-6 Manual page 279

OBUFTDS
Primitive: 3-State Output Buffer with Differential Signaling, Active-Low Output Enable
Introduction
This design element is an output buffer that supports low-voltage, differential signaling. For the OBUFTDS,
a design level interface signal is represented as two distinct ports (O and OB), one deemed the "master" and
the other the "slave." The master and the slave are opposite phases of the same logical signal (for example,
MYNET_P and MYNET_N).
Logic Table
Inputs
I T
X 1
0 0
1 0
Port Descriptions
Port Direction
O Output
OB Output
I Input
T Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
IOSTANDARD String
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Outputs
O
Z
0
1
Width
1
1
1
1
Allowed Values Default
See Data Sheet "DEFAULT"
www.xilinx.com
Chapter 4: About Design Elements
OB
Z
1
0
Function
Diff_p output (connect directly to top level port)
Diff_n output (connect directly to top level port)
Buffer input
3-state enable input
Recommended
No
No
No
Description
Assigns an I/O standard to the element.
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