Xilinx Virtex-6 Manual page 315

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM64M: 64-deep by 4-wide Multi Port LUT RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM64M_inst : RAM64M
generic map (
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000)
port map (
DOA => DOA, -- Read port A 1-bit output
DOB => DOB, -- Read port B 1-bit output
DOC => DOC, -- Read port C 1-bit output
DOD => DOD, -- Read/Write port D 1-bit output
ADDRA => ADDRA, -- Read port A 6-bit address input
ADDRB => ADDRB, -- Read port B 6-bit address input
ADDRC => ADDRC, -- Read port C 6-bit address input
ADDRD => ADDRD, -- Read/Write port D 6-bit address input
DIA => DIA, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRA
DIB => DIB, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRB
DIC => DIC, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRC
DID => DID, -- RAM 1-bit data write input addressed by ADDRD,
-- read addressed by ADDRD
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM64M_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- Initial contents of A port
-- Initial contents of B port
-- Initial contents of C port
-- Initial contents of D port
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