Xilinx Virtex-6 Manual page 380

Chapter 4: About Design Elements
USR_ACCESS_VIRTEX6
Primitive: Virtex-6 User Access Register
Introduction
This design element enables access to a 32-bit register within the configuration logic. You will thus be able to
read the data from the bitstream. One use for this component is to allow data stored in bitstream storage source
to be accessed by the FPGA design after configuration.
Port Descriptions
Port Direction
CFGCLK Output
DATA[31:0] Output
DATAVALID Output
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- USR_ACCESS_VIRTEX6: Configuration Data Access
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
USR_ACCESS_VIRTEX6_inst : USR_ACCESS_VIRTEX6
port map (
CFGCLK => CFGCLK,
DATA => DATA,
DATAVALID => DATAVALID
);
-- End of USR_ACCESS_VIRTEX6_inst instantiation
380
Width Function
1 Configuration Clock output
32 Configuration Data output
1 Active high DATA port contains valid data
-- 1-bit output: Configuration Clock output
-- 32-bit output: Configuration Data output
-- 1-bit output: Active high data valid output
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013