Xilinx Virtex-6 Manual page 358

Chapter 4: About Design Elements
INITB =>INITB, -- 1-bit bi-directional INIT status pin
M => M, -- 3-bit input Mode pins
PROGB => PROGB, -- 1-bit input Program pin
RDWRB => RDWRB -- 1-bit input Read/Write pin
);
-- End of SIM_CONFIG_V6_inst instantiation
Verilog Instantiation Template
// SIM_CONFIG_V6: Behavioral Simulation-only Model of FPGA SelectMap Configuration
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
SIM_CONFIG_V6 #(
.DEVICE_ID(32'h00000000), // Specify DEVICE_ID
.ICAP_SUPPORT("FALSE"),
.ICAP_WIDTH("X8")
) SIM_CONFIG_V6_inst (
.BUSY(BUSY), // 1-bit output Busy pin
.CSOB(CSOB), // 1-bit output chip select pin
.DONE(DONE), // 1-bit bi-directional Done pin
.CCLK(CCLK), // 1-bit input configuration clock
.CSB(CSB), // 1-bit input chip select
.D(D), // 32-bit bi-directional configuration data
.INITB(INITB), // 1-bit bi-directional INIT status pin
.M(M), // 3-bit input Mode pins
.PROGB(PROGB), // 1-bit input Program pin
.RDWRB(RDWRB) // 1-bit input Read/write pin
);
// End of SIM_CONFIG_V6_inst instantiation
For More Information
• See the Synthesis and Simulation Design Guide
• See the Virtex-6 FPGA User Documentation (User Guides and Data
358
// Using ICAP, "TRUE" or "FALSE"
// ICAP width, "X8", "X16", "X32"
// Do not need to change/specify if ICAP_SUPPORT="FALSE"
(UG626).
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Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013