Xilinx Virtex-6 Manual page 178

Chapter 4: About Design Elements
Data
Attribute Type
IDELAY_TYPE String"
IDELAY_VALUE Integer
ODELAY_TYPE String
Integer
ODELAY_VALUE
REFCLK_ 1
FREQUENCY significant
digit
FLOAT
SIGNAL_PATTERN String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IODELAYE1: Input and Output Fixed or Variable Delay Element
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IODELAYE1_inst : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "I",
HIGH_PERFORMANCE_MODE => TRUE, -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
IDELAY_TYPE => "DEFAULT",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA"
)
port map (
CNTVALUEOUT => CNTVALUEOUT, -- 5-bit output - Counter value for monitoring purpose
DATAOUT => DATAOUT,
C => C,
CE => CE,
CINVCTRL => CINVCTRL,
178
Allowed Values Default
"DEFAULT", "FIXED", "DEFAULT"
"VARIABLE",
VAR_LOADABLE"
0, 1, 2, 3, 4, 5, 6, 7, 8, 0
9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27,
28, 29, 30, 31
"FIXED, "VARIABLE", "FIXED"
"VAR_LOADABLE"
0, 1, 2, 3, 4, 5, 6, 7, 8, 0
9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27,
28, 29, 30, 31
190.0 to 210.1 and 200.0
290.0 to 310.0
"DATA", "CLOCK" "DATA"
-- Enable dynamic clock inversion ("TRUE"/"FALSE")
-- Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
-- "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
-- Input delay tap setting (0-32)
-- "FIXED", "VARIABLE", or "VAR_LOADABLE"
-- Output delay tap setting (0-32)
-- IDELAYCTRL clock input frequency in MHz
-- "DATA" or "CLOCK" input signal
-- 1-bit output - Delayed data output
-- 1-bit input - Clock input
-- 1-bit input - Active high enable increment/decrement function
-- 1-bit input - Dynamically inverts the Clock (C) polarity
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Description
consumption is quantified in the Xilinx Power
Estimator (XPE) tool.
Sets the type of tap delay line. DEFAULT delay
guarantees zero hold times. FIXED delay
sets a static delay value. VAR_LOADABLE
dynamically loads tap values. VARIABLE
delay dynamically adjusts the delay value.
Specifies the fixed number of delay taps in
fixed mode or the initial starting number of
taps in VARIABLE mode (input path). When
IDELAY_TYPE is set to VAR_LOADABLE
mode, this value is ignored.
Specifies a fixed, variable or default (eliminate
hold time) output delay.
Specifies the fixed number of delay taps in
fixed mode or the initial starting number of
taps in VARIABLE mode (output path). When
IDELAY_TYPE is set to VAR_LOADABLE
mode, this value is ignored.
Sets the tap value (in MHz) used by the
timing analyzer for static timing analysis and
functional/timing simulation. The frequency
of REFCLK must be within the given datasheet
range to guarantee the tap-delay value and
performance.
Causes the timing analyzer to account for the
appropriate amount of delay-chain jitter in the
data or clock path.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013