Xilinx Virtex-6 Manual page 169

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
-- Set, Reset and Clock Enable.
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IDDR_2CLK_inst : IDDR_2CLK
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => Q1, -- 1-bit output for positive edge of clock
Q2 => Q2, -- 1-bit output for negative edge of clock
C => C, -- 1-bit primary clock input
CB => CB, -- 1-bit secondary clock input
CE => CE, -- 1-bit clock enable input
D => D, -- 1-bit DDR data input
R => R, -- 1-bit reset
S => S -- 1-bit set
);
-- End of IDDR_2CLK_inst instantiation
Verilog Instantiation Template
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
// Set, Reset and Clock Enable.
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_2CLK_inst (
.Q1(Q1), // 1-bit output for positive edge of clock
.Q2(Q2), // 1-bit output for negative edge of clock
.C(C), // 1-bit primary clock input
.CB(CB), // 1-bit secondary clock input
.CE(CE), // 1-bit clock enable input
.D(D), // 1-bit DDR data input
.R(R), // 1-bit reset
.S(S) // 1-bit set
);
// End of IDDR_2CLK_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- or "SAME_EDGE_PIPELINED"
// or "SAME_EDGE_PIPELINED"
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Chapter 4: About Design Elements
169