Xilinx Virtex-6 Manual page 330

Chapter 4: About Design Elements
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_A, INIT_B: Initial values on output ports
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
-- READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
READ_WIDTH_A => 0,
READ_WIDTH_B => 0,
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 0,
-- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
-- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_A => X"00000",
SRVAL_B => X"00000",
-- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 16-bit (each) output: Port A data
DOADO => DOADO,
DOPADOP => DOPADOP,
-- Port B Data: 16-bit (each) output: Port B data
DOBDO => DOBDO,
DOPBDOP => DOPBDOP,
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
-- when RAM_MODE="SDP")
ADDRARDADDR => ADDRARDADDR,
CLKARDCLK => CLKARDCLK,
ENARDEN => ENARDEN,
REGCEAREGCE => REGCEAREGCE,
RSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit input: A port set/reset input
RSTREGARSTREG => RSTREGARSTREG, -- 1-bit input: A port register set/reset input
WEA => WEA,
-- Port A Data: 16-bit (each) input: Port A data
DIADI => DIADI,
DIPADIP => DIPADIP,
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
-- when RAM_MODE="SDP")
ADDRBWRADDR => ADDRBWRADDR,
CLKBWRCLK => CLKBWRCLK,
ENBWREN => ENBWREN,
REGCEB => REGCEB,
RSTRAMB => RSTRAMB,
RSTREGB => RSTREGB,
WEBWE => WEBWE,
-- Port B Data: 16-bit (each) input: Port B data
DIBDI => DIBDI,
DIPBDIP => DIPBDIP
);
-- End of RAMB18E1_inst instantiation
330
-- 16-bit output: A port data/LSB data output
-- 2-bit output: A port parity/LSB parity output
-- 16-bit output: B port data/MSB data output
-- 2-bit output: B port parity/MSB parity output
-- 14-bit input: A port address/Read address input
-- 1-bit input: A port clock/Read clock input
-- 1-bit input: A port enable/Read enable input
-- 1-bit input: A port register enable/Register enable input
-- 2-bit input: A port write enable input
-- 16-bit input: A port data/LSB data input
-- 2-bit input: A port parity/LSB parity input
-- 14-bit input: B port address/Write address input
-- 1-bit input: B port clock/Write clock input
-- 1-bit input: B port enable/Write enable input
-- 1-bit input: B port register enable input
-- 1-bit input: B port set/reset input
-- 1-bit input: B port register set/reset input
-- 4-bit input: B port write enable/Write enable input
-- 16-bit input: B port data/MSB data input
-- 2-bit input: B port parity/MSB parity input
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-- RAM init file
-- "SDP" or "TDP"
-- "PERFORMANCE" or
-- "DELAYED_WRITE"
-- 0,1,2,4,9,18,36
-- 0,1,2,4,9,18
-- 0,1,2,4,9,18
-- 0,1,2,4,9,18,36
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013