Xilinx Virtex-6 Manual page 38

Chapter 2: About Unimacros
Name Direction
LOAD_DATA Input
RST Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
WIDTH_PREADD
WIDTH_MULTIPLIER
WIDTH_PRODUCT
LATENCY
DEVICE
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ADDMACC_MACRO_inst : ADDMACC_MACRO
generic map (
DEVICE => "VIRTEX6",
LATENCY => 4,
38
Width
Variable, see WIDTH_PRODUCT
attribute.
1
Data Type Allowed Values
Integer 1 to 24
Integer 1 to 18
Integer 1 to 48
Integer 0, 1, 2, 3, 4
String "VIRTEX6",
"SPARTAN6"
-- Target Device: "VIRTEX6", "SPARTAN6"
-- Desired clock cycle latency, 1-4
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Function
In a DSP slice, when LOAD is asserted, loads P
with A*B+LOAD_DATA.
Synchronous Reset
Yes
No
No
Recommended
Default Description
24 Controls the width of PREADD1
and PREADD2 inputs.
18
Controls the width of MULTIPLIER
input.
48 Controls the width of MULTIPLIER
output.
3 Number of pipeline registers
• 1 - MREG == 1
• 2 - AREG == BREG == 1 and
MREG == 1 or MREG == 1 and
PREG == 1
• 3 - AREG == BREG == 1 and
MREG == 1 and PREG == 1
• 4 - AREG == BREG == 2 and
MREG == 1 and PREG == 1
"VIRTEX6" Target hardware architecture.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013