Xilinx Virtex-6 Manual page 294

Chapter 4: About Design Elements
Verilog Instantiation Template
// PULLUP: I/O Buffer Weak Pull-up
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
PULLUP PULLUP_inst (
.O(O) // Pullup output (connect directly to top-level port)
);
// End of PULLUP_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).
Virtex-6 Libraries Guide for HDL Designs
294 www.xilinx.com UG623 (v 14.5) March 20, 2013