Xilinx Virtex-6 Manual page 327

Data
Attribute Type
DOB_REG Integer
INIT_A Hexa-
decimal
INIT_B Hexa-
decimal
INIT_FILE String
INIT_00 - INIT_3F Hexa-
decimal
INITP_00 - INITP_07 Hexa-
decimal
RAM_MODE
String
RDADDR_ String
COLLISION
_HWCONFIG
READ_WIDTH_A Integer
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
0, 1 0
Any 18 Bit Value All zeros
Any 18 Bit Value All zeros
String representing None
file name and location
All zeros to all ones All zeros
All zeros to all ones All zeros
"TDP", "SDP" "TDP"
"DELAYED_WRITE", "DELAYED_WRITE"•
"PERFORMANCE"
0, 1, 2, 4, 9, 18, 36, 72 0
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Chapter 4: About Design Elements
Description
A value of 1 enables the output
registers to the RAM enabling quicker
clock-to-out from the RAM at the
expense of an added clock cycle of
read latency. A value of 0 allows a
read in one clock cycle but will result
in slower clock-to-out timing. Applies
to port B in TDP mode and upper bits
(including parity bits) in SDP mode.
Specifies the initial value on the Port
A output after configuration. Applies
to port A in TDP mode and up to 18
lower bits (including parity bits) in
SDP mode.
Specifies the initial value on the Port
B output after configuration. Applies
to port B in TDP mode and upper bits
(including parity bits) in SDP mode.
File name of file used to specify initial
RAM contents.
Allows specification of the initial
contents of the 16 kb data memory
array.
Allows specification of the initial
contents of the 2 kb parity data
memory array.
Selects simple dual port (SDP) or true
dual port (TDP) mode.
Setting to "PERFORMANCE"
allows for higher clock
performance (frequency) in
READ_FIRST mode.
• If using the same clock on
both ports of the RAM with
"PERFORMANCE" mode, the
address overlap collision rules
apply.
• In "DELAYED_WRITE" mode, you
can safely use the BRAM without
incurring collisions.
• Not supported for ES silicon and
must be set to "DELAYED_WRITE"
if targeting ES devices.
Specifies the desired data width for a
read on Port A, including parity bits.
This value must be 0 if the Port A is not
used. Otherwise, it should be set to the
desired port width. In SDP mode, this
is the read width including parity bits.
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