Xilinx Virtex-6 Manual page 119

.USE_MULT("MULTIPLY"),
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(1),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(1),
.CARRYINSELREG(1),
.CREG(1),
.DREG(1),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(1),
.PREG(1),
.USE_SIMD("ONE48")
)
DSP48E1_inst (
// Cascade: 30-bit (each) output: Cascade Ports
.ACOUT(ACOUT),
.BCOUT(BCOUT),
.CARRYCASCOUT(CARRYCASCOUT),
.MULTSIGNOUT(MULTSIGNOUT),
.PCOUT(PCOUT),
// Control: 1-bit (each) output: Control Inputs/Status Bits
.OVERFLOW(OVERFLOW),
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
.PATTERNDETECT(PATTERNDETECT),
.UNDERFLOW(UNDERFLOW),
// Data: 4-bit (each) output: Data Ports
.CARRYOUT(CARRYOUT),
.P(P),
// Cascade: 30-bit (each) input: Cascade Ports
.ACIN(ACIN),
.BCIN(BCIN),
.CARRYCASCIN(CARRYCASCIN),
.MULTSIGNIN(MULTSIGNIN),
.PCIN(PCIN),
// Control: 4-bit (each) input: Control Inputs/Status Bits
.ALUMODE(ALUMODE),
.CARRYINSEL(CARRYINSEL),
.CEINMODE(CEINMODE),
.CLK(CLK),
.INMODE(INMODE),
.OPMODE(OPMODE),
.RSTINMODE(RSTINMODE),
// Data: 30-bit (each) input: Data Ports
.A(A),
.B(B),
.C(C),
.CARRYIN(CARRYIN),
.D(D),
// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
.CEA1(CEA1),
.CEA2(CEA2),
.CEAD(CEAD),
.CEALUMODE(CEALUMODE),
.CEB1(CEB1),
.CEB2(CEB2),
.CEC(CEC),
.CECARRYIN(CECARRYIN),
.CECTRL(CECTRL),
.CED(CED),
.CEM(CEM),
.CEP(CEP),
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
// Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
// "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
// 48-bit mask value for pattern detect (1=ignore)
// 48-bit pattern match for pattern detect
// "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
// Select pattern value ("PATTERN" or "C")
// Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
// Number of pipeline stages for pre-adder (0 or 1)
// Number of pipeline stages for ALUMODE (0 or 1)
// Number of pipeline stages for A (0, 1 or 2)
// Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
// Number of pipeline stages for B (0, 1 or 2)
// Number of pipeline stages for CARRYIN (0 or 1)
// Number of pipeline stages for CARRYINSEL (0 or 1)
// Number of pipeline stages for C (0 or 1)
// Number of pipeline stages for D (0 or 1)
// Number of pipeline stages for INMODE (0 or 1)
// Number of multiplier pipeline stages (0 or 1)
// Number of pipeline stages for OPMODE (0 or 1)
// Number of pipeline stages for P (0 or 1)
// SIMD selection ("ONE48", "TWO24", "FOUR12")
// 30-bit output: A port cascade output
// 18-bit output: B port cascade output
// 1-bit output: Cascade carry output
// 1-bit output: Multiplier sign cascade output
// 48-bit output: Cascade output
// 1-bit output: Overflow in add/acc output
// 1-bit output: Pattern detect output
// 1-bit output: Underflow in add/acc output
// 4-bit output: Carry output
// 48-bit output: Primary data output
// 30-bit input: A cascade data input
// 18-bit input: B cascade input
// 1-bit input: Cascade carry input
// 1-bit input: Multiplier sign input
// 48-bit input: P cascade input
// 4-bit input: ALU control input
// 3-bit input: Carry select input
// 1-bit input: Clock enable input for INMODEREG
// 1-bit input: Clock input
// 5-bit input: INMODE control input
// 7-bit input: Operation mode input
// 1-bit input: Reset input for INMODEREG
// 30-bit input: A data input
// 18-bit input: B data input
// 48-bit input: C data input
// 1-bit input: Carry input signal
// 25-bit input: D data input
// 1-bit input: Clock enable input for 1st stage AREG
// 1-bit input: Clock enable input for 2nd stage AREG
// 1-bit input: Clock enable input for ADREG
// 1-bit input: Clock enable input for ALUMODERE
// 1-bit input: Clock enable input for 1st stage BREG
// 1-bit input: Clock enable input for 2nd stage BREG
// 1-bit input: Clock enable input for CREG
// 1-bit input: Clock enable input for CARRYINREG
// 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
// 1-bit input: Clock enable input for DREG
// 1-bit input: Clock enable input for MREG
// 1-bit input: Clock enable input for PREG
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Chapter 4: About Design Elements
119