Xilinx Virtex-6 Manual page 198

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT1_D: 1-input Look-Up Table with general and local outputs
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT1_D_inst : LUT1_D
generic map (
INIT => "00")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0 -- LUT input
);
-- End of LUT1_D_inst instantiation
Verilog Instantiation Template
// LUT1_D: 1-input Look-Up Table with general and local outputs
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT1_D #(
.INIT(2'b00) // Specify LUT Contents
) LUT1_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0) // LUT input
);
// End of LUT1_D_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
198
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013