Xilinx Virtex-6 Manual page 134

Chapter 4: About Design Elements
Verilog Instantiation Template
// FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
FIFO18E1 #(
.ALMOST_EMPTY_OFFSET(13'h0080),
.ALMOST_FULL_OFFSET(13'h0080),
.DATA_WIDTH(4),
.DO_REG(1),
.EN_SYN("FALSE"),
.FIFO_MODE("FIFO18"),
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to TRUE or FALSE
.INIT(36'h000000000),
.SRVAL(36'h000000000)
)
FIFO18E1_inst (
// Read Data: 32-bit (each) output: Read output data
.DO(DO),
.DOP(DOP),
// Status: 1-bit (each) output: Flags and other FIFO status outputs
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: almost empty output flag
.ALMOSTFULL(ALMOSTFULL),
.EMPTY(EMPTY),
.FULL(FULL),
.RDCOUNT(RDCOUNT),
.RDERR(RDERR),
.WRCOUNT(WRCOUNT),
.WRERR(WRERR),
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
.RDCLK(RDCLK),
.RDEN(RDEN),
.REGCE(REGCE),
.RST(RST),
.RSTREG(RSTREG),
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
.WRCLK(WRCLK),
.WREN(WREN),
// Write Data: 32-bit (each) input: Write input data
.DI(DI),
.DIP(DIP)
);
// End of FIFO18E1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
134
// Sets the almost empty threshold
// Sets almost full threshold
// Sets data width to 4, 9, 18, or 36
// Enable output register (0 or 1) Must be 1 if EN_SYN = FALSE
// Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
// Sets mode to FIFO18 or FIFO18_36
// Initial values on output port
// Set/Reset value for output port
// 32-bit output: data output
// 4-bit output: parity data output
// 1-bit output: almost full output flag
// 1-bit output: empty output flag
// 1-bit output: full output flag
// 12-bit output: read count output
// 1-bit output: read error output
// 12-bit output: write count output
// 1-bit output: write error
// 1-bit input: read clock input
// 1-bit input: read enable input
// 1-bit input: clock enable input
// 1-bit input: reset input
// 1-bit input: output register set/reset
// 1-bit input: write clock input
// 1-bit input: write enable input
// 32-bit input: data input
// 4-bit input: parity input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013