Page 1
Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011 www.BDTIC.com/XILINX...
Page 2
Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.
Table 3-30, page 170, revised the description of TRANS_TIME_RATE. • Revised PCI Express Clocking Use Mode, page 170 and added Figure 3-29, page 171 Figure 3-30, page 172. www.BDTIC.com/XILINX UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide...
Page 4
• Added the RX_EN_REALIGN_RESET_BUF2 attribute to Table 4-53, page 262. • Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 4-58, page 270. Appendix • Added new appendix. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 5
RX_DLYALIGN_OVRDSETTING in Table 4-41. Updated Using the RX Phase Alignment Circuit to Bypass the Buffer, page 235, including Note 2 in Notes for Figure 4-32.. Updated Figure 4-33. www.BDTIC.com/XILINX UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide...
Page 6
Reference Clock Checklist. Added Reference Clock Toggling. 10/01/10 Updated Functional Description, GTX TX Reset in Response to Completion of Configuration, GTX TX Reset in Response to GTXTXRESET Pulse. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 7
Bypass: TX delay aligner bypassed, additional requirements on interconnect logic clocking use model; Updated RX Buffer Bypass: RX delay aligner bypassed for lower line rates, higher line rate support is an advanced feature. www.BDTIC.com/XILINX UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide...
Page 8
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
• Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver. • GTXE1 is the name of the instantiation primitive that instantiates one Virtex-6 FPGA GTX transceiver. • A Quad or Q is a cluster or set of four GTX transceivers that share two differential reference clock pin pairs and analog supply pins.
• Virtex-6 FPGA PCB Designer’s Guide This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers, with a focus on strategies for making design decisions at the PCB and interface level. Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm.
Virtex-6 FPGA GTX Transceiver Wizard). The GTX transceiver offers a data rate range and features that allow physical layer support for various protocols. Figure 1-1 illustrates a block view of the Virtex-6 FPGA GTX transceiver. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com...
Page 20
Buffer sampling SIPO RX-PMA RX-PCS UG366_c1_01_051509 Figure 1-1: Virtex-6 FPGA GTX Transceiver Simplified Block Diagram Details about the different functional blocks of the transmitter and receiver including their use models are described in Chapter 3, Transmitter, and Chapter 4, Receiver.
Page 21
Overview • The Virtex-6 FPGA Configuration User Guide provides more information on the Configuration and Clock, MMCM, and I/O blocks. • The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailed information on the Ethernet MAC. Figure 1-2 illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T FPGA.
GTX transceiver primitive called GTXE1. The Wizard can be found in the CORE Generator tool. Be sure to download the most up-to-date IP Update before using the Wizard. Details on how to use this Wizard can be found in Virtex-6 FPGA GTX T ransceiver Getting Started Guide.
The Synthesis and Simulation Design Guide explains how to set up the simulation environment for supported simulators depending on the used Hardware Description Language (HDL). This design guide can be downloaded from the Xilinx website. The prerequisites for simulating a design with GTX transceivers are: •...
RXSTATUS[2:0] = 011 reports that an RX port is connected. FALSE (default): Simulates a disconnected TX port. TXDETECTRX initiates receiver detection, and RXSTATUS[2:0] = 000 reports that an RX port is not connected. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
The default for this attribute is 1.0. SIM_GTXRESET_SPEEDUP The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of the TX PMA PLL and the RX PMA PLL. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
For multi-rate designs requiring the reference clock source driving the TX PMA PLL to be changed on the fly, the TXPLLREFSELDY port is used to dynamically select the reference clock source instead. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
0, 1, x, or z. The default for this attribute is x. Implementation Functional Description This section provides the information needed to map Virtex-6 FPGA GTX transceivers instantiated in a design to device resources, including: •...
LX240T: Not available MGTRXN0_118 LX365T: Not available LX550T: GTXE1_X0Y32 SX315T: Not available MGTTXP0_118 SX475T: GTXE1_X0Y32 MGTTXN0_118 UG366_c1_15_051509 Figure 1-15: Placement Diagram for the FF1759 Package (1 of 9) www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 53
MGTTXN1_117 MGTRXP0_117 LX240T: GTXE1_X0Y20 MGTRXN0_117 LX365T: GTXE1_X0Y20 LX550T: GTXE1_X0Y28 SX315T: GTXE1_X0Y20 MGTTXP0_117 SX475T: GTXE1_X0Y28 MGTTXN0_117 UG366_c1_16_051509 Figure 1-16: Placement Diagram for the FF1759 Package (2 of 9) www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 54
MGTTXN1_116 MGTRXP0_116 LX240T: GTXE1_X0Y16 MGTRXN0_116 LX365T: GTXE1_X0Y16 LX550T: GTXE1_X0Y24 SX315T: GTXE1_X0Y16 MGTTXP0_116 SX475T: GTXE1_X0Y24 MGTTXN0_116 UG366_c1_17_051509 Figure 1-17: Placement Diagram for the FF1759 Package (3 of 9) www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 55
MGTTXN1_115 MGTRXP0_115 LX240T: GTXE1_X0Y12 MGTRXN0_115 LX365T: GTXE1_X0Y12 LX550T: GTXE1_X0Y20 SX315T: GTXE1_X0Y12 MGTTXP0_115 SX475T: GTXE1_X0Y20 MGTTXN0_115 UG366_c1_18_051509 Figure 1-18: Placement Diagram for the FF1759 Package (4 of 9) www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 56
MGTTXN1_114 MGTRXP0_114 LX240T: GTXE1_X0Y8 MGTRXN0_114 LX365T: GTXE1_X0Y8 LX550T: GTXE1_X0Y16 SX315T: GTXE1_X0Y8 MGTTXP0_114 SX475T: GTXE1_X0Y16 MGTTXN0_114 UG366_c1_19_051509 Figure 1-19: Placement Diagram for the FF1759 Package (5 of 9) www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 57
MGTTXN1_113 MGTRXP0_113 LX240T: GTXE1_X0Y4 MGTRXN0_113 LX365T: GTXE1_X0Y4 LX550T: GTXE1_X0Y12 SX315T: GTXE1_X0Y4 MGTTXP0_113 SX475T: GTXE1_X0Y12 MGTTXN0_113 UG366_c1_20_051509 Figure 1-20: Placement Diagram for the FF1759 Package (6 of 9) www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 58
MGTTXN1_112 MGTRXP0_112 LX240T: GTXE1_X0Y0 MGTRXN0_112 LX365T: GTXE1_X0Y0 LX550T: GTXE1_X0Y8 SX315T: GTXE1_X0Y0 MGTTXP0_112 SX475T: GTXE1_X0Y8 MGTTXN0_112 UG366_c1_21_051509 Figure 1-21: Placement Diagram for the FF1759 Package (7 of 9) www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 59
LX240T: Not available MGTRXN0_111 LX365T: Not available LX550T: GTXE1_X0Y4 SX315T: Not available MGTTXP0_111 SX475T: GTXE1_X0Y4 MGTTXN0_111 UG366_c1_22_051509 Figure 1-22: Placement Diagram for the FF1759 Package (8 of 9) www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 60
LX240T: Not available MGTRXN0_110 LX365T: Not available LX550T: GTXE1_X0Y0 SX315T: Not available MGTTXP0_110 SX475T: GTXE1_X0Y0 MGTTXN0_110 UG366_c1_23_051509 Figure 1-23: Placement Diagram for the FF1759 Package (9 of 9) www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
(Pad) mapped to MGTREFCLK0P/MGTREFCLK0N and MGTREFCLK1P/MGTREFCLK1P. This is the active-Low asynchronous clock enable signal for the clock buffer. Pulling this signal High powers down the clock buffer. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
GTX transceivers provide several available reference clock inputs. Clock selection and availability changed slightly across the first three generations of Virtex® FPGA transceivers. The Virtex-6 FPGA GTX transceiver significantly enhances reference clock capabilities by adding dedicated clock routing and multiplexer resources. Architecturally, the concept of a Quad (or Q), contains a grouping of four GTXE1 primitives, two dedicated reference clock pin pairs, and dedicated reference clock routing.
Page 103
Reference Clock Selection document describes the reference clocking architecture of the Virtex-6 FPGA GTX transceivers. Reference clock features include: • Clock routing for north and south bound clocks. • Clock inputs available per GTX PLL. • Static or dynamic selection of the reference clock for the transmitter and receiver PLLs.
Page 105
A single reference clock is most commonly used. In this case, the TXPLLREFSELDY and RXPLLREFSELDY ports can be connected to 000, and the Xilinx software tools handle the complexity of the multiplexers and associated routing. See Single External Reference Clock Use Model for more information.
GTX TXPLLREFSELDY and RXPLLREFSELDY ports. The dedicated reference clock routing between Quads is set by the Xilinx software tools in both single and multiple reference clock modes.
Page 107
RXPLLREFSELDY port. SIM_TXREFCLK_SOURCE[2:0] 3-bit Binary Simulation control for the GTX reference clock selection. This attribute is set to the same binary value as the TXPLLREFSELDY port. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
User Constraints File (UCF). For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. The simulation-only attributes must be set on the GTXE1 primitive to match the clock input used.
Page 109
Figure 2-5 is a simplification. The output port ODIV2 is left floating, and the input port CEB is set to logic 0. The Xilinx implementation tools make the necessary adjustments to the north/south routing shown in Figure 2-2 as well as pin swapping necessary to the GTX clock inputs to route clocks from one Quad to another when required.
IBUFDS_GTXE1 primitive to use these dedicated reference clock resources. For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. For the first external reference clock, the user design connects the MGTREFCLK0[P/N] IBUFDS_GTXE1 output (O) to the MGTREFCLKRX[0] and MGTREFCLKTX[0] ports of the GTXE1 primitive.
Page 111
TX PLL and RX PLL of each transceiver can be sourced by either MGTREFCLK0[P/N] or MGTREFCLK1[P/N]. Users can set TXPLLREFSELDY[2:0] and RXPLLREFSELDY[2:0] to the corresponding value as shown in Figure 2-3, page 105. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 112
Quad by using the NORTHREFCLK and SOUTHREFCLK ports. The Xilinx software tools handle the complexity of the multiplexers and associated routing for designs that require a single reference clock per GTX transceiver PLL.
The PLL has a nominal operation range between 1.2 to 2.7 GHz for -1 speed grade devices and 1.2 to 3.3 GHz for -2 and -3 speed -grade devices. Refer to the Virtex-6 FPGA Data Sheet for the operating limits. The PLL output has a divider that can divide the output frequency by one, two, or four.
Page 114
(Gb/s). D is the PLL output divider that resides in the clock divider block. PLLClkout Equation 2-2 ---------------------------------- - LineRate Table 2-7 lists the actual attribute and commonly used divider values. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
2, 4, 5 RXPLL_DIVSEL_FB TXPLL_DIVSEL_OUT 1, 2, 4 RXPLL_DIVSEL_OUT The Virtex-6 FPGA GTX transceiver allows the N1 divider to be set independently from the PCS internal datapath width. This allows additional flexibility in reference clock selection. Ports and Attributes Table 2-8 defines the PLL ports.
Page 116
Chapter 2: Shared Transceiver Features Table 2-9: PLL Attributes (Cont’d) Attribute Type Description TX_TDCC_CFG 2-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Binary Transceiver Wizard. TXPLL_COM_CFG 24-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard.
Page 119
16 or 20. • Performance impact needs to be carefully considered if a reference clock below the typical recommended frequency is used. Refer to the Virtex-6 FPGA Data Sheet for the minimum and maximum reference clock frequencies. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com...
10: P1 (longer recovery time; Receiver Detection still on) 11: P2 (lowest power state) Attributes can control the transition times between these power-down states. Table 2-12 defines the power-down attributes. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Using the RX Phase Alignment Circuit to Bypass the Buffer, page 235. 1'b0: Use the RX Delay Aligner 1'b1: Bypass the RX Delay Aligner All other bits are reserved. Use recommended values from the Virtex-6 FPGA GTX Transceiver Wizard. TRANS_TIME_FROM_P2 12-bit Counter settings for programmable transition time from P2 state for PCIe operation.
RXPLLPOWERDOWN must be tied Low. Refer to TX Buffer Bypass, page 155 for more information. When bypassing the RX buffer, all of these requirements must be met: www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Functional Description Loopback modes are specialized configurations of the transceiver datapath where the traffic stream is folded back to the source. Typically, a specific traffic pattern is transmitted www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Virtex-6 FPGA GTX Transceiver Wizard. ACJTAG Functional Description The Virtex-6 FPGA GTX transceiver supports ACJTAG, as specified by IEEE Std 1149.6. To ensure reliable ACJTAG operation, the GTX RX expects the swing coming in to be 800 mV (400 mV ) or higher.
DRP of the first transceiver in the Quad. The first transceiver in the Quad has the lowest Y coordinates. Refer to Implementation, page 41 for details on transceiver placement and numbering. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship based on the TX_DATA_WIDTH setting. Table 3-4 shows the relationship between TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH values. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
This port is used to synchronize the FPGA logic with the TX interface. This clock must be positive-edge aligned to TXUSRCLK when TXUSRCLK is provided by the user. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
(TX_DATA_WIDTH = 16 or 20). The GEN_TXUSRCLK attribute is set to “TRUE”, and the TXUSRCLK input port is tied to ground. TXUSRCLK is internally generated for the internal TX PCS datapath. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
UG366_c3_23_061609 Figure 3-2: TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode) Refer to the Virtex-6 FPGA Data Sheet for the maximum clock frequency and jitter limitations of BUFR. For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide.
FPGA TX Interface Refer to the Virtex-6 FPGA Data Sheet for the maximum clock frequency and jitter limitations of BUFR. For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide.
Figure 3-5: TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode) For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. TXOUTCLK Driving More Than One GTX TX in 4-Byte Mode (Multiple...
Figure 3-6: TXOUTCLK Driving More Than One GTX TX in 4-Byte Mode For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. TXOUTCLK Driving More Than One GTX TX in 1-Byte Mode (Multiple...
UG366_c3_22_061509 Figure 3-7: TXOUTCLK Driving More Than One GTX TX in 1-Byte Mode For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. TX Initialization Functional Description The GTX TX must be reset before it can be used.
Page 137
The circuit must follow the timing diagram shown in Figure 3-9. X-Ref Target - Figure 3-9 GTXTEST[1] TXPLLLKDET / RXPLLLKDET 1024 CLKs CLKs CLKs CLKs UG366_c3_33_092410 Figure 3-9: Transmitter Reset After Configuration www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Attribute Type Description TX_EN_RATE_RESET_BUF Boolean When set to TRUE, this attribute enables automatic TX buffer reset during a rate change event initiated by a change in TXRATE[1:0]. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 141
TX Delay Aligner, TX Phase TXDLYALIGNRESET, Alignment, TX PCS TXRESET Notes: 1. The recommended reset has the smallest impact on the other components of the GTX transceiver. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
TX PCS in reset until the clock source is locked again. If the TX buffer is bypassed and phase alignment is in use, phase alignment must be performed again after the clock source relocks. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Inverts normal running disparity when encoding TXDATA Forces running disparity negative when encoding TXDATA Forces running disparity positive when encoding TXDATA Ports and Attributes Table 3-12 defines the TX encoder ports. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 145
TX_DATA_WIDTH must be set to 10, 20, or 40 when the 8B/10B encoder is enabled. 0: 8B/10B encoder bypassed. This option reduces latency. 1: 8B/10B encoder enabled. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
The TX gearbox only supports 2-byte and 4-byte interfaces. A 1-byte interface is not supported. Scrambling of the data is done in the FPGA logic. The Virtex-6 FPGA GTX Transceiver Wizard has example code for the scrambler.
TX gearbox. This continues for the third and fourth cycle. On the fifth cycle, the output of the TX gearbox contains two remaining data bits from the first 66-bit block, the www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
The second mode uses an internal sequence counter. The TX gearbox only supports 2-byte and 4-byte interfaces to the FPGA logic. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
8777acf1 7c580498 4e1fea87 5714e976 523cd413 53365af5 4e658bf8 d3892141 c1a9308d Pause for 1 USRCLK2 cycle. Data is ignored. UG366_c3_05_051509 Figure 3-15: Pause at Sequence Counter Value 31 www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 150
After applying 4 bytes of data, the counter increments to 2 and drives data on TXDATA and header information on TXHEADER. On count 31, stop the data pipeline. On count 32, drive data on TXDATA. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
High on the cycle where new data must be driven. For this mode of operation, the number of hold points is identical to when using the external sequence counter mode for 64B/67B and 64B/66B. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 152
TXUSRCLK2 cycles for a 2-byte input). On the next TXUSRCLK2 cycle, drive data on the TXDATA inputs. TXGEARBOXREADY is asserted High on the previous TXUSRCLK2 cycle. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
The phase-alignment circuit can be used to reduce the skew between Lane Deskew separate GTX transceivers. All GTX transceivers involved must use the same line rate. Oversampling The TX buffer is required for oversampling. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
When oversampling is enabled (OVERSAMPLE_MODE = TRUE), the TX buffer is used for bit interpolation and must always be active. See TX Oversampling, page 166 for more information about built-in 5X oversampling. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
TX Buffer Bypass Functional Description Bypassing the TX buffer is an advanced feature of the Virtex-6 FPGA GTX transceivers. The TX phase-alignment circuit is used to adjust the phase difference between the PMA parallel clock domain (XCLK) and the TXUSRCLK domain when the TX buffer is bypassed.
Page 156
TXPMASETPHASE is High. TXUSRCLK Use this port to provide a clock for the internal TX PCS datapath. The rate for TXUSRCLK depends on TX_DATA_WIDTH. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 157
Use or bypass the TX buffer. TRUE: Use the TX buffer (normal mode). FALSE: Bypass the TX buffer (advanced feature). TX_BYTECLK_CFG[5:0] 6-bit Hex Reserved. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard. TX_DATA_WIDTH Integer Sets the transmitter external data width...
Table 3-20: Number of Required TXUSRCLK2 Clock Cycles for Driving TXPMASETPHASE High TXPLL_DIVSEL_OUT TXUSRCLK2 Wait Cycles 8,192 16,384 32,767 The phase-alignment procedure must be redone if any of the following conditions occur: www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
For non PCI Express mode, a “SYNC_DONE” user signal, which behaves like USER_PHYSTATUS, can be asserted to indicate TX phase-alignment completion. Figure 3-22 shows the TX phase alignment after a rate change. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Clocks Are the Same Clock Edge Independent GTX TX GTX TX Before After Phase Alignment Phase Alignment UG366_c3_12_051509 Figure 3-23: TX Phase Alignment Circuit to Reduce Lane Skew www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Figures Figure 3-2 Figure 3-5 describe the clocking use model with BUFG and BUFR. Figures Figure 3-3 Figure 3-6 describe the clocking use model with MMCM. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Error insertion function is supported to verify link connection and also for jitter tolerance test. When inverted PRBS pattern is necessary, use TXPOLARITY signal to control polarity. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 163
PCI Express Compliance Pattern Square Wave with 2 UI Period Square Wave with 16 UI or 20 UI Period TXDATA UG366_c3_15_051110 Figure 3-25: TX Pattern Generator Block www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
For link quality testing, choose test pattern by setting TXENPRBSTST and RXENPRBSTST to non-000, and set RXPRBSERR_LOOPBACK to 0 (Figure 3-26). Only the PRBS pattern is recognized by the RX pattern checker. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 165
Checker PRBS-7 Pattern with Jitter RX_PRBS_ERR_CNT RXPRBSERR_LOOPBACK = 1 TXENPRBSTST TX Pattern Generator Pattern Checker TXPRBSFORCEERR UG366_c3_17_061809 Figure 3-27: Jitter Tolerance Test Mode with a PRBS-7 Pattern www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
1: Inverted. TXP is negative, and TXN is positive. There are no TX polarity control attributes. Using TX Polarity Control If the TXP/TXN differential traces are swapped on a board, tie TXPOLARITY High. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
IBUFDS_GTXE1 is a redundant output for additional clocking scheme flexibility. The RX PLL resides in the RX portion of the same GTX transceiver. It can be used in place of the TX PLL for low-power operation. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
• /5 is selected when the internal data width is 20 For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. Serial Clock Divider Each transmitter PMA module has a D divider that divides down the clock from the PLL for lower line rate support.
TX PLL input reference clock or other internal clocks to be output to the FPGA logic. TXOUTCLKPCS Async TXOUTCLKPCS is a redundant output. TXOUTCLK with TXOUTCLK_CTRL = “TXOUTCLKPCS” should be used instead. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Table 3-30: TX Fabric Clock Output Control Attributes Attribute Type Description TRANS_TIME_RATE 8-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard. This attribute determines when PHYSTATUS and TXRATEDONE are asserted after a rate change. TX_EN_RATE_RESET_BUF Boolean When set to TRUE, this attribute enables automatic TX buffer reset during a rate change event initiated by a change in TXRATE.
CEB is set to logic 0. For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. Rate Change Use Mode for PCI Express 2.0 Operation In PCI Express mode, TXRATE[1] must be tied to 1, and TXRATE[0] is used for line rate change.
TX Configurable Driver Functional Description The GTX TX driver is a high-speed current-mode differential output buffer. To maximize signal integrity, it includes these features: • Differential voltage control www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
TX de-emphasis control for PCI Express PIPE interface. This signal is mapped internally to TXPOSTEMPHASIS via attributes. 0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute) 1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute) www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 176
This attribute has the value of TXPOSTEMPHASIS[4:0] that has to be Binary mapped when TXDEEMPH = 1. TX_DEEMPH_1[4:0] = TXPOSTEMPHASIS[4:0]. The default is 10000 (nominal value). Do not modify this value. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 177
TXDIFFCTRL[3:0] that has to be mapped when TXMARGIN = 001 and TXSWING = 1. TX_MARGIN_LOW_1 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0]. The default is 7’b1000100 (445 mV typical). Do not modify this value. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
This is used in a backplane situation where the presets (TX_MARGIN_*_*, TXSWING) correspond to different slot numbers. Use Mode – Resistor Calibration For more information on the on-chip resistor calibration, refer to Termination Resistor Calibration Circuit, page 274. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
PHY functions, including power management state transitions and receiver detection. When this signal transitions during entry and exit from P2 and RXUSRCLK2 is not running, the signaling is asynchronous. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
COM sequences to be changed based on the divider settings used for the TX line rate. Note: The GTX transceiver transmits the ALIGNp primitive character within each OOB burst pulse at the current line rate operation. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Virtex-6 FPGA GTX Transceiver Wizard. The GTX transceiver supports four signaling modes: three for SATA/SAS operations and one for PCI Express operations. The use of these mechanisms is mutually exclusive. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 182
Chapter 3: Transmitter www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
FALSE when using AC coupling. TRUE: MGTAVTT_* reference for receiver termination activated. FALSE: MGTAVTT_* reference for receiver termination disabled. Use Modes – RX Termination for valid RX Termination combinations. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Use Mode Swing Suggested Protocols and Usage Notes Voltage Coupling Bias Coupling 800 mV 1200 Protocol: PCIe Attribute Settings: AC_CAP_DIS = FALSE RCV_TERM_GND = TRUE RCV_TERM_VTTRX = FALSE www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 187
Xilinx FPGA SerDes interface. In this configuration, the signal swing from the cable equalizer device is usually less than 1200 mV. Attribute Settings: AC_CAP_DIS = TRUE RCV_TERM_GND = FALSE RCV_TERM_VTTRX = TRUE www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Figure 4-7: RX Termination Use Mode 5 Configuration Use Mode – Resistor Calibration For more information on the on-chip resistor calibration, refer to Termination Resistor Calibration Circuit, page 274. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
1: OOB signal detected. The differential voltage is below the minimum threshold. 0: OOB signal not detected. The differential voltage is above the minimum threshold. This port is intended for PCI Express and SATA standards. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 193
SAS/SATA SATA_MAX_WAKE 6-bit Hex Upper bound on idle count during COMWAKE for SAS/SATA SATA_MIN_BURST 6-bit Hex Lower bound on an activity burst for COM FSM for SAS/SATA www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
6-bit Hex Lower bound on idle count during COMWAKE for SAS/SATA Notes: 1. These are OOB nominal values. Consult the Virtex-6 FPGA Data Sheet for OOB specifications. RX Equalizer Functional Description The RX has a continuous time RX equalization circuit and a decision feedback equalization circuit to compensate for high-frequency losses in the channel.
Page 195
It is a 4-tap architecture. X-Ref Target - Figure 4-11 Linear 16 or 20 SIPO Termination DIV4 / DIV5 UG366_c4_10_051509 Figure 4-11: DFE in the GTX RX www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 196
The optimization criteria for the TAP values and the DFECLK delay is the vertical eye opening. The DFETAPOVRD port switches off auto-calibration and overrides the TAP values, and the DFEDLYOVRD port overrides the DFECLK delay. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
1-bit sign). For example, –2 is represented as 1 0010. DFETAP3[3:0] RXUSRCLK2 DFE tap 3 weight value control for each transceiver (3-bit resolution plus 1-bit sign). For example, –2 is represented as 1 010. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 198
15 dB at Nyquist), it is recommended that RX_EN_IDLE_HOLD_DFE should be set to FALSE because fast transitioning data patterns like the 101010 sequence in CJPAT/CJTPAT can accidentally trigger an electrical idle www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
(trace length neglected) + 20 inches [508 mm] on line cards. Use Mode – Auto-To-Fix This is an advance feature. Use Mode – Auto This is an advance feature. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Type Description CDR_PH_ADJ_TIME 5-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Binary Transceiver Wizard. This attribute defines the delay after deassertion of the CDR phase reset before the optional reset sequence of PCI Express operation is complete during electrical idle.
Page 206
This divider defines the nominal line rate for the receiver. It can be set to 1, 2, or 4. RX Line Rate = RX PLL Clock * 2/PLL_RXDIVSEL_OUT www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
The selection of the /4 or /5 divider block is dependent on RX_DATA_WIDTH (see Table 4-56, page 269): • /4 is selected when the internal data width is 16 • /5 is selected when the internal data width is 20 www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
The control for the serial divider is described in Table 4-23. For details about the line rate range per speed grade, refer to the Virtex-6 FPGA Data Sheet. Table 4-23: RX PLL Output Divider Setting Line Rate Range D Divider...
RXRATE[1:0] = 00. Otherwise the D divider value is controlled by RXRATE[1:0]. Valid settings are: 1: Set the D divider to 1 2: Set the D divider to 2 4: Set the D divider to 4 www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
RX data must be synchronous to the RX REFCLK.) The CDR can be frozen by setting the lowest 11 bits of the PMA_RX_CFG attribute to zero (PMA_RX_CFG[10:0] = 11’b0). www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 211
FPGA user logic or user software. This mode is only recommended for diagnostic purposes because the received user data is corrupted due to the non-optimal sampling position. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
DFEEYEDACMON[4:0] RXUSRCLK2 Average vertical eye height (voltage domain) used by the DFE as an optimization criterion. 11111: Indicates approximately 200 mV of internal eye opening. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
1: Inverted. RXP is negative and RXN is positive. There are no RX polarity control attributes. Using RX Polarity Control If the polarity of RXP/RXN needs to be inverted, RXPOLARITY must be tied High. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Activating and operating the oversampling block The GTX Transceiver Wizard automatically configures the GTX transceiver and makes the oversampling ports available when generating a GTX wrapper with oversampling enabled. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
The RXENPRBSTST entry in Table 4-31 shows the available settings. When the PRBS checker is running, it attempts to find the selected PRBS pattern in the incoming www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Figure 4-21: Conceptual View of Alignment (Aligning to a 10-Bit Comma) Figure 4-22 shows the TX parallel data is on the left side, and the RX receiving recognizable parallel data is on the right side. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
If COMMA_DOUBLE is TRUE, the MCOMMA and PCOMMA patterns are combined so that the block searches for two commas in a row. The number of bits in the comma depends www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
If alignment is still activated for the comma that arrives, the block automatically aligns the new comma to the closest boundary and drives RXBYTEREALIGN High for one RXUSRCLK2 cycle. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
RXSLIDE must be Low for at least 16 RXUSRCLK2 cycles before it can be used again. Figure 4-27 shows the waveforms for manual alignment using RXSLIDE in RX_SLIDE_MODE = PCS before and after the data shift. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 221
Slide Results on RXDATA After Several Cycles of Latency RXDATA 00000000000000010000 00000000000000100000 00000000000001000000 TXDATA 00000000000000010000 UG366_c4_27_103010 Figure 4-27: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Aligns the byte boundary when comma minus is detected. 0: Disabled 1: Enabled RXENPCOMMAALIGN RXUSRCLK2 Aligns the byte boundary when comma plus is detected. 0: Disabled 1: Enabled www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 223
This attribute is a 10-bit mask with a default value of 1111111111. Any bit in the mask that is reset to 0 effectively turns the corresponding bit in MCOMMA or PCOMMA to a don't care bit. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 224
FALSE: Do not bring the realignment comma to the FPGA RX. This setting reduces the RX datapath latency. TRUE: Bring the realignment comma to the FPGA RX. SHOW_REALIGN_COMMA = TRUE should not be used when COMMA_DOUBLE = TRUE. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 225
RXUSRCLK clock cycles) before checking the alignment again. Valid settings are from 0 to 15. The default value is 5. Only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard should be used. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com...
RX_LOS_THRESHOLD attributes. RX_LOS_THRESHOLD adjusts how sensitive the LOS state machine is to bad characters (RX_LOS_THRESHOLD divided by RX_LOS_INVALID_INCR) to change the machine from the SYNC_ACQUIRED state to the www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
High when a channel bonding sequence has been written into the RX elastic buffer. TRUE: Loss of sync FSM is in operation and its state is reflected on RXLOSSOFSYNC[1]. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
H 1 G 1 F 1 E 1 D 1 C 1 B 1 A 1 H 0 G 0 F 0 E 0 D 0 C 0 B 0 A 0 RXDATA 8B/10B Received Received Last First UG366_c4_26_051509 Figure 4-29: RX Interface with 8B/10B Decoding www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
X-Ref Target - Figure 4-30 RXUSRCLK2 Good Disp Out of Both Good RXDATA Data Error Table Errors Data RXDISPERR RXNOTINTABLE UG366_c4_27_051509 Figure 4-30: RX Data with 8B/10B Errors www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
RXUSRCLK2 RXRUNDISP shows the running disparity of the 8B/10B encoder when RXDATA is received. RXRUNDISP[3] corresponds to RXDATA[31:24] RXRUNDISP[2] corresponds to RXDATA[23:16] RXRUNDISP[1] corresponds to RXDATA[15:8] RXRUNDISP[0] corresponds to RXDATA[7:0] www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
RX Buffer Bypass Functional Description Bypassing the RX buffer is an advanced feature of the Virtex-6 FPGA GTX transceivers. RX buffer bypass can operate only under certain system-level conditions. The RX phase-alignment circuit is used to adjust the phase difference between the PMA parallel clock domain (XCLK) and the RXUSRCLK domain when the RX buffer is bypassed.
MGTAVCC must be supplied to these transceivers. Refer to Managing Unused GTX Transceivers, page 276 for more information. Ports and Attributes Table 4-40 defines the RX buffer bypass ports. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 233
RX PLL input reference clock or the recovered clocks to be output to fabric. RXUSRCLK Use this port to provide a clock for the internal RX PCS datapath. The rate for RXUSRCLK depends on RX_DATA_WIDTH. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 234
16/20: 2 byte interface 32/40: 4 byte interface If 8B10B is used, this attribute must be a multiple of 10. RX_DLYALIGN_CTRINC 4-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Binary Transceiver Wizard. RX_DLYALIGN_EDGESET 5-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Binary Transceiver Wizard.
RXPLLREFCLK_DIV2 (DRP value 100) OFF_LOW (DRP value 101) OFF_HIGH (DRP value 110) RXUSRCLK_DLY 16-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard. PMA_RXSYNC_CFG 7-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX Transceiver Wizard.
Page 236
Any number of clock cycles can be used for the CDR lock time, but using a larger number decreases the number of cycles through the states. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 237
32 RXUSRCLK2 Cycles to Phase Align Fail Validate Data Received at Fabric Interface Pass Phase Alignment Done UG366_c4_30_122810 Figure 4-33: Steps Required for Successful RX Phase Alignment www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Buffer latency depends on features used (clock Lower deterministic latency than using the correction and channel bonding) RX elastic buffer Clock Correction / Required for clock correction / channel Channel Bonding bonding www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Determines count value after which an assertion of reset due to Binary RX_EN_IDLE_RESET_BUF is triggered after valid data is no longer present on the RXP/RXN lines. Use the Virtex-6 FPGA GTX Transceiver Wizard default. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com...
Determines count value after which a deassertion of reset due to Binary RX_EN_IDLE_RESET_BUF is triggered after valid data once again present on the RXP/RXN lines. Use the Virtex-6 FPGA GTX Transceiver Wizard default. RX_XCLK_SEL String Selects the clock used to drive the RX parallel clock domain (XCLK).
001: Number of bytes in the buffer are less than CLK_COR_MIN_LAT 010: Number of bytes in the buffer are greater than CLK_COR_MAX_LAT 101: RX elastic buffer underflow 110: RX elastic buffer overflow www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 242
Specifies the maximum RX elastic buffer latency. If the RX elastic buffer exceeds CLK_COR_MAX_LAT, the clock correction circuit removes incoming clock correction sequences to prevent overflow. Valid values for this attribute range from 3 to 48. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 243
CLK_COR_SEQ_1_ENABLE can be used to make parts of the sequence don't cares. If CLK_COR_SEQ_1_ENABLE[k] is 0, CLK_COR_SEQ_1_k is a don't care subsequence and is always considered to be a match. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 244
K characters and disparity information is used. Bit ordering of the 8B/10B output is used. FALSE: Sequences are matched against non-encoded data. Bit ordering is as for an non-encoded parallel interface. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Figure 4-36 shows how to set a clock correction sequence byte when RX_DECODE_SEQ_MATCH is TRUE. When RX_DECODE_SEQ_MATCH is FALSE, the sequence must exactly match non- encoded incoming data. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
RXDATA has the first byte of a clock correction sequence that was replicated and added to the RX elastic buffer. To use the RXRUNDISP port to indicate inserted idles instead of the current RX running disparity, CLK_COR_INSERT_IDLE_FLAG is set to TRUE. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
This signal goes Low if an unaligned channel bonding sequence is detected, indicating that channel alignment was lost. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 248
This port cannot be driven High at the same time as RXCHBONDMASTER. RXENCHANSYNC RXUSRCLK2 This port enables channel bonding (from the FPGA logic to both the master and slaves). Table 4-49 defines the RX channel bonding attributes. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 249
Determines if the second channel bonding sequence is to be used. TRUE: Channel bonding can be triggered by channel bonding sequence 1 or 2. FALSE: Channel bonding is only triggered by sequence 1. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
GTX transceivers, one transceiver is set to Master. The remaining GTX transceivers in the group are set to Slaves. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 252
12 GTX transceivers are channel bonded together, the use of additional clock pins is required as well as using the same oscillator (see Figure 2-5, page 109). www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
CLK_COR_PRECEDENCE must be set to TRUE. To make channel bonding a higher priority, CLK_COR_PRECEDENCE must be set to FALSE. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
The RX gearbox encounters similar data and header pauses found in the TX gearbox. Figure 4-46 shows such a pause in addition to RXHEADERVALID asserting every other cycle and RXDATAVALID being deasserted for one cycle. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
When using the RX Gearbox, a block synchronization state machine is required in the FPGA logic. Figure 4-47 shows the operation of a block synchronization state machine. The Virtex-6 FPGA GTX Transceiver Wizard has example code for this type of module. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 259
RESET_CNT where all counters are zeroed out. The synchronization header is analyzed in the TEST_SH state. If the header is valid, sh_cnt is incremented in the VALID_SH state, otherwise sh_count and sh_invalid_count are incremented in the INVALID_SH state. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 260
Closely spaced slip pulses. State machine Slip data asserts slip as soon as it sees bad header. alignment RXDATAVALID0 RXGEARBOXSLIP0 RXHEADER0 RXHEADERVALID0 RXSTARTOFSEQ0 UG366_c4_45_051509 Figure 4-48: RX Gearbox with Block Synchronization www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
GTX RX. PLLRXRESET Async This port resets the RX PLL of the GTX RX. PRBSCNTRESET RXUSRCLK2 This port resets the PRBS error counter. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 262
If this attribute is FALSE, the RX elastic buffer reset upon realignment occurs only when the received signal from RXP/RXN is determined valid and RXELECIDLE = 0. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Figure 4-51 assumes that the frequency of the internal clock is 50 MHz with default values for the configuration attributes. The entire GTX RX is affected by GTXRXRESET. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Each component-level reset signal is described in Table 4-54. All receiver component resets are asynchronous with the exception of PRBSCNTRESET, which is synchronous to RXUSRCLK2. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Page 265
RX Analog Front End RX OOB RX Equalizer RX PMA RX PLL RX CDR SIPO Loopback Loopback Paths Table 4-55 lists the recommended resets for various situations. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
The reference clock source(s) and the power to the GTX transceiver(s) must be available before configuring the FPGA. The reference clock must be stable before configuration especially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators). www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
RX CDR can be pulled out of lock by the apparent sudden change in frequency. When the guidelines in Link Idle Reset Support, page 264 are followed, the electrical idle reset situation is automatically managed. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
PRBSCNTRESET is asserted to reset the PRBS error counter. After an Oversampler Error If RXOVERSAMPLEERR goes High to indicate an overflow or underflow in the oversampling block FIFO, asserting RXRESET clears it. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Interface Width Configuration The Virtex-6 FPGA GTX transceiver contains an internal 2-byte datapath. The FPGA interface width is configurable by setting the RX_DATA_WIDTH attribute. When the 8B/10B decoder is enabled, the FPGA interface must be configured to 10, 20, or 40 bits.
RXUSRCLK2. RXUSRCLK2 and RXUSRCLK have a fixed-rate relationship based on the RX_DATA_WIDTH setting. Table 4-59 shows the relationship between RXUSRCLK2 and RXUSRCLK per RX_DATA_WIDTH values. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
If clock correction is used, RXUSRCLK and RXUSRCLK2 can be sourced by RXRECCLK or TXOUTCLK. For details about placement constraints and restrictions on clocking resources (MMCM, BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources User Guide. Ports and Attributes Table 4-60 defines the FPGA RX ports.
Page 272
RX_DATA _WIDTH must be set to 10, 20, or 40. Valid settings are 8, 10, 16, 20, 32, and 40. Interface Width Configuration, page 269 for more details. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Differential clock input pin pair for the reference clock of the Quad. MGTREFCLK1N (Pad) MGTRREF Calibration resistor input pin for the termination resistor calibration circuit. See (Pad) Termination Resistor Calibration Circuit, page 274 for more information. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
MGTTXP2/MGTTXN2 MGTTXP3/MGTTXN3 Figure 5-1 shows the connections of the power supply pins for the GTX transceiver. The listed voltages are nominal values. Refer to the Virtex-6 FPGA Data Sheet for values and operating conditions. X-Ref Target - Figure 5-1 Quad 1.0V...
Page 275
Trace length from the resistor pins to the FPGA pins MGTRREF and MGTAVTTRCAL Connection must be equal in length to AVTT 100Ω MGTRREF MGTAVTTRCAL UG366_c5_03_051509 Figure 5-3: PCB Layout for the RCAL Resistor www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
GTX transceivers that affect such things as power consumption of the Virtex-6 FPGA. When considering which Quads to use in an application, the organization of the package power planes needs to be taken into account.
MGTAVCC_S MGTAVTT_S UG366_c5_04_051509 Figure 5-4: GTX Power Plane Bank Orientation in Virtex-6 FPGA Packages Unused Quad Column If none of the Quads in a column are used in the application, the Quad device pins can be connected as shown in Table 5-3.
Quad pins can be connected. For the first scenario, if the Virtex-6 FPGA is one of the devices with a north bank and a south bank of Quads and none of the devices in the south bank are used in the application,...
RCAL precision resistor Quad Usage Priority If only a portion of the Quads in a Virtex-6 FPGA are used, they should be used based on their priority. The higher priority Quads should be used before the lower priority Quads. The prioritization of the Quads is determined by package size. Because the smaller...
These characteristics are selection criteria when choosing an oscillator for a GTX transceiver design. Figure 5-5 illustrates the convention for the single-ended clock input voltage swing, peak- to-peak as used in the GTX transceiver portion of the Virtex-6 FPGA Data Sheet. X-Ref Target - Figure 5-5 MGTREFCLKP...
Page 281
4/5 of MGTAVCC, or nominal 0.8V. MGTAVCC is nominally 1.0V, hence the common mode voltage is nominally 800 mV. The resistor values given in Figure 5-8 nominal. Refer to the Virtex-6 FPGA Data Sheet for exact specifications. X-Ref Target - Figure 5-8 MGTREFCLKP 50Ω...
• Ensure that the differential voltage swing of the reference clock is the range as specified in the Virtex-6 FPGA Data Sheet (the nominal range is 200 mV – 2000 mV, and the typical value is 1200 mV). Note: These are nominal values.
Some packages contain two planes (a north plane and a south plane) for each of the analog power supplies. See Analog www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Some, not all, linear regulators provide noise rejection at the output from noise present on the voltage input. The linear regulator usually requires a minimal number of external components to realize a circuit on the PCB. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Switching regulators generate significant noise and therefore usually require additional filtering before the voltage is delivered to the GTX analog power supply input of the Virtex-6 FPGA. The amplitude of the noise should be limited to less than 10 mV PK-PK Therefore the power supply filter should be designed to attenuate the noise from the switching regulator so that it meets this requirement.
Package Additional decoupling is in the Virtex-6 FPGA packages. Decoupling capacitors in the package provide attenuation for noise in the package power plane, thereby reducing the interaction between Quads. These capacitors in the package also help to maintain a low- impedance, high-frequency path between the power supply (MGTAVCC or MGTAVTT) and ground.
PCB. Board Stackup For Virtex-6 FPGA GTX transceivers, the board stackup layers can be grouped into power distribution layers and signal routing layers. The power distribution layer group connects the power supply sources for MGTAVCC and MGTAVTT to the power supply pins on the Virtex-6 FPGA.
GTX transceiver region of the Virtex-6 FPGA and how to avoid exposure to the SelectIO interface region of the Virtex-6 FPGA BGA pin field. It also shows how filter capacitors discussed in...
Layer 1 to Layer 3 is that the traces on both layers use the plane on Layer 2 as the return current reference plane. www.BDTIC.com/XILINX Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011...
Page 290
Figure 5-15. The Virtex-6 FPGA packages have been designed with grounds adjacent to all of the GTX transceiver signal pins. Having adjacent ground pins leads to adjacent BGA breakout vias. The adjacent ground vias provide a return current path for the signal via as the signal propagates from one layer to another layer in the stackup.
FPGA is already powered and configured, i.e., hot-swappable or hot-pluggable. The Virtex-6 FPGA GTX transceivers support hot swapping. The Virtex-6 FPGA transceivers continue to function if the far-end receiver or transmitter is removed or installed. A recommended practice for hot-pluggable devices is to use a connector with staged pins so that the ground pins make contact prior to the other connector pins.
Page 292
The power islands for the GTX transceivers are also a potential source for SelectIO interface induced noise. SelectO interface signals should not be routed over the GTX power islands. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Note: Do NOT modify the Reserved bits! Attributes that are not described explicitly are set automatically by the Virtex-6 FPGA GTX Transceiver Wizard. These attributes must be left at their defaults, except for use cases that explicitly request different values.
1. The DRP has the same binary encoding value as the attribute encoding value. 2. The receiver has to be operational for this DRP register to take effect. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide UG366 (v2.5) January 17, 2011...
Need help?
Do you have a question about the Virtex-6 FPGA and is the answer not in the manual?
Questions and answers