Xilinx Virtex-6 Manual page 47

Available Attributes
Attribute Data Type
RESET_UPON_TC Boolean
DEVICE String
DIRECTION String
COUNT_BY Hexa-
decimal
TC_VALUE Hexa-
decima
WIDTH_DATA Integer
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
COUNTER_TC_MACRO_inst : COUNTER_TC_MACRO
generic map (
COUNT_BY => X"000000000001", -- Count by value
DEVICE => "VIRTEX6",
DIRECTION => "UP",
RESET_UPON_TC => "FALSE",
TC_VALUE => X"000000000000", -- Terminal count value
WIDTH_DATA => 48)
port map (
Q => Q, -- Counter output, width determined by WIDTH_DATA generic
TC => TC, -- 1-bit terminal count output, high = terminal count is reached
CLK => CLK, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
RST => RST -- 1-bit active high synchronous reset
);
-- End of COUNTER_TC_MACRO_inst instantiation
Verilog Instantiation Template
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
COUNTER_TC_MACRO #(
.COUNT_BY(48'h000000000001), // Count by value
.DEVICE("VIRTEX6"),
.DIRECTION("UP"),
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
.TC_VALUE(48'h000000000000), // Terminal count value
.WIDTH_DATA(48)
) COUNTER_TC_MACRO_inst (
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
.CLK(CLK), // 1-bit positive edge clock input
.CE(CE), // 1-bit active high clock enable input
.RST(RST) // 1-bit active high synchronous reset
);
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
True, False False
"VIRTEX6", "VIRTEX6"
"SPARTAN6"
"UP", "DOWN" "UP"
Any 48 bit value 000000000001
Any 48 bit value All zeros
1-48 48
-- Target Device: "VIRTEX5", "VIRTEX6"
-- Counter direction "UP" or "DOWN"
-- Reset counter upon terminal count, TRUE or FALSE
-- Counter output bus width, 1-48
// Target Device: "VIRTEX5", "VIRTEX6"
// Counter direction, "UP" or "DOWN"
// Counter output bus width, 1-48
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Chapter 2: About Unimacros
Description
Specifies whether to reset the counter
upon reaching terminal count
Target hardware architecture.
Count up versus count down.
Count by n; takes precedence over
WIDTH_DATA
Terminal count value.
Specifies counter width.
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