Xilinx Virtex-6 Manual page 293

PULLUP
Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
Introduction
This design element allows for an input, 3-state output or bi-directional port to be driven to a weak high
value when not being driven by an internal or external source. This element establishes a High logic level for
open-drain elements and macros when all the drivers are off.
Port Descriptions
Port Direction
O Output
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- PULLUP: I/O Buffer Weak Pull-up
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
PULLUP_inst : PULLUP
port map (
O => O -- Pullup output (connect directly to top-level port)
);
-- End of PULLUP_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1 Pullup output (connect directly to top level port)
Yes
No
No
No
www.xilinx.com
Chapter 4: About Design Elements
293