Xilinx Virtex-6 Manual page 150

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
DIFF_TERM
Boolean TRUE or FALSE
IOSTANDARD String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDS: Differential Input Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
I => I, -- Diff_p buffer input (connect directly to top-level port)
IB => IB -- Diff_n buffer input (connect directly to top-level port)
);
-- End of IBUFDS_inst instantiation
Verilog Instantiation Template
// IBUFDS: Differential Input Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IBUFDS #(
.DIFF_TERM("FALSE"),
.IOSTANDARD("DEFAULT")
) IBUFDS_inst (
.O(O), // Buffer output
.I(I), // Diff_p buffer input (connect directly to top-level port)
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFDS_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
150
Allowed
Values Default
FALSE
See Data Sheet. "DEFAULT"
// Differential Termination
// Specify the input I/O standard
www.xilinx.com
Description
Enables the built-in differential termination
resistor.
Assigns an I/O standard to the element.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013