Xilinx Virtex-6 Manual page 304

Chapter 4: About Design Elements
RAM32X1D
Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous RAM
Introduction
The design element is a 32-word by 1-bit static dual port random access memory with synchronous write
capability. The device has two separate address ports: the read address (DPRA4:DPRA0) and the write address
(A4:A0). These two address ports are completely asynchronous. The read address controls the location of
the data driven out of the output pin (DPO), and the write address controls the destination of a valid write
transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data
stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the
data input (D) into the word selected by the 5-bit write address. For predictable performance, write address and
data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High
WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into
the block. You can initialize RAM32X1D during configuration using the INIT attribute. Mode selection is
shown in the following logic table.
The SPO output reflects the data in the memory cell addressed by A4:A0. The DPO output reflects the data in
the memory cell addressed by DPRA4:DPRA0. The write process is not affected by the address on the read
address port.
Logic Table
Inputs
WE (Mode) WCLK
X
0 (read)
0
1 (read)
1
1 (read)
↑
1 (write)
↓
1 (read)
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
304
Outputs
D SPO
X
data_a
X
data_a
X
data_a
D D
X data_a
Yes
Recommended
No
No
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com
DPO
data_d
data_d
data_d
data_d
data_d
UG623 (v 14.5) March 20, 2013